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i#1569 AArch64: Fix bug in encoding (SIMD structure load/store). #2527

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Jul 12, 2017
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i#1569 AArch64: Fix bug in encoding (SIMD structure load/store). #2527

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1399dfb
i#1569 AArch64: Fix bug in encoding (SIMD structure load/store).
egrimley-arm Jul 6, 2017
2347a5b
Merge branch 'master' into i1569-x16imm
egrimley-arm Jul 12, 2017
4e39546
Add test case.
egrimley-arm Jul 12, 2017
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5 changes: 2 additions & 3 deletions core/arch/aarch64/codec.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2205,10 +2205,9 @@ encode_opnd_x16imm(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_ou
return true;
} else if (opnd_is_immed_int(opnd)) {
ptr_int_t bytes = opnd_get_immed_int(opnd);
int regs = multistruct_regcount(enc);
if (bytes != regs * 8 && bytes != regs * 16)
if (bytes != (8 << extract_uint(enc, 30, 1)) * multistruct_regcount(enc))
return false;
*enc_out = 31U << 16 | (uint)(bytes == regs * 16) << 30;
*enc_out = 31U << 16;
return true;
}
return false;
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3 changes: 2 additions & 1 deletion core/arch/aarch64/codec.py
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Expand Up @@ -135,7 +135,8 @@ def generate_encoder(patterns, opndsgen, opndtypes):
vars = (['dst%d' % i for i in range(len(dsts))] +
['src%d' % i for i in range(len(srcs))])
c += [' int opcode = instr->opcode;']
c += [' uint ' + ', '.join(vars) + ';']
# The initial values are only required to silence a bad compiler warning:
c += [' uint ' + ' = 0, '.join(vars) + ' = 0;']
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I think it would be cleaner to add the initialisers in a separate commit.

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You're probably right.

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Separate pull request for initialisers: #2528

tests = (['instr_num_dsts(instr) == %d && instr_num_srcs(instr) == %d' %
(len(dsts), len(srcs))] +
['encode_opnd_%s(enc & 0x%08x, opcode, '
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50 changes: 33 additions & 17 deletions core/arch/aarch64/codec.txt
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Expand Up @@ -100,7 +100,7 @@
-----------xxxxx---------------- x16p0 # even-numbered X register (or XZR)
-----------xxxxx---------------- x16p1 # ... add 1
-----------xxxxx---------------- x16immvr # computes immed from 21, 13 and 11:10
-----------xxxxx---------------- x16immvs # computes immed 21, 15:13 and 11:10
-----------xxxxx---------------- x16immvs # computes immed from 21, 15:13 and 11:10
-----------xxxxxxxxx------------ mem9off # immed offset for mem9/mem9post
-----------xxxxxxxxx--xxxxx----- mem9 # gets size from 31:30
-----------xxxxxxxxx--xxxxx----- mem9q # size is 16 bytes
Expand Down Expand Up @@ -134,7 +134,7 @@
-x-----------------x------------ index2 # index of S subreg in Q: 0-3
-x-----------------xx----------- index1 # index of H subreg in Q: 0-7
-x-----------------xxx---------- index0 # index of B subreg in Q: 0-15
-x---------xxxxx---------------- x16imm # computes immed from 30 and 15:12
-----------xxxxx---------------- x16imm # computes immed from 30 and 15:12
x--------------------------xxxxx wx0 # W/X register (or WZR/XZR)
x--------------------------xxxxx wx0sp # W/X register or WSP/XSP
x---------------------xxxxx----- wx5 # W/X register (or WZR/XZR)
Expand Down Expand Up @@ -737,21 +737,37 @@ x0110111xxxxxxxxxxxxxxxxxxxxxxxx tbnz tbz

## Advanced SIMD load/store multiple structures (post-indexed)

0x001100100xxxxx0000xxxxxxxxxxxx st4 memvm x5sp : vmsz vt0 vt1 vt2 vt3 x5sp x16imm
0x001100100xxxxx0010xxxxxxxxxxxx st1 memvm x5sp : vmsz vt0 vt1 vt2 vt3 x5sp x16imm
0x001100100xxxxx0100xxxxxxxxxxxx st3 memvm x5sp : vmsz vt0 vt1 vt2 x5sp x16imm
0x001100100xxxxx0110xxxxxxxxxxxx st1 memvm x5sp : vmsz vt0 vt1 vt2 x5sp x16imm
0x001100100xxxxx0111xxxxxxxxxxxx st1 memvm x5sp : vmsz vt0 x5sp x16imm
0x001100100xxxxx1000xxxxxxxxxxxx st2 memvm x5sp : vmsz vt0 vt1 x5sp x16imm
0x001100100xxxxx1010xxxxxxxxxxxx st1 memvm x5sp : vmsz vt0 vt1 x5sp x16imm

0x001100110xxxxx0000xxxxxxxxxxxx ld4 vt0 vt1 vt2 vt3 x5sp : memvm vmsz x5sp x16imm
0x001100110xxxxx0010xxxxxxxxxxxx ld1 vt0 vt1 vt2 vt3 x5sp : memvm vmsz x5sp x16imm
0x001100110xxxxx0100xxxxxxxxxxxx ld3 vt0 vt1 vt2 x5sp : memvm vmsz x5sp x16imm
0x001100110xxxxx0110xxxxxxxxxxxx ld1 vt0 vt1 vt2 x5sp : memvm vmsz x5sp x16imm
0x001100110xxxxx0111xxxxxxxxxxxx ld1 vt0 x5sp : memvm vmsz x5sp x16imm
0x001100110xxxxx1000xxxxxxxxxxxx ld2 vt0 vt1 x5sp : memvm vmsz x5sp x16imm
0x001100110xxxxx1010xxxxxxxxxxxx ld1 vt0 vt1 x5sp : memvm vmsz x5sp x16imm
00001100100xxxxx0000xxxxxxxxxxxx st4 memvm x5sp : vmsz vt0 vt1 vt2 vt3 x5sp x16imm
00001100100xxxxx0010xxxxxxxxxxxx st1 memvm x5sp : vmsz vt0 vt1 vt2 vt3 x5sp x16imm
00001100100xxxxx0100xxxxxxxxxxxx st3 memvm x5sp : vmsz vt0 vt1 vt2 x5sp x16imm
00001100100xxxxx0110xxxxxxxxxxxx st1 memvm x5sp : vmsz vt0 vt1 vt2 x5sp x16imm
00001100100xxxxx0111xxxxxxxxxxxx st1 memvm x5sp : vmsz vt0 x5sp x16imm
00001100100xxxxx1000xxxxxxxxxxxx st2 memvm x5sp : vmsz vt0 vt1 x5sp x16imm
00001100100xxxxx1010xxxxxxxxxxxx st1 memvm x5sp : vmsz vt0 vt1 x5sp x16imm

00001100110xxxxx0000xxxxxxxxxxxx ld4 vt0 vt1 vt2 vt3 x5sp : memvm vmsz x5sp x16imm
00001100110xxxxx0010xxxxxxxxxxxx ld1 vt0 vt1 vt2 vt3 x5sp : memvm vmsz x5sp x16imm
00001100110xxxxx0100xxxxxxxxxxxx ld3 vt0 vt1 vt2 x5sp : memvm vmsz x5sp x16imm
00001100110xxxxx0110xxxxxxxxxxxx ld1 vt0 vt1 vt2 x5sp : memvm vmsz x5sp x16imm
00001100110xxxxx0111xxxxxxxxxxxx ld1 vt0 x5sp : memvm vmsz x5sp x16imm
00001100110xxxxx1000xxxxxxxxxxxx ld2 vt0 vt1 x5sp : memvm vmsz x5sp x16imm
00001100110xxxxx1010xxxxxxxxxxxx ld1 vt0 vt1 x5sp : memvm vmsz x5sp x16imm

01001100100xxxxx0000xxxxxxxxxxxx st4 memvm x5sp : vmsz vt0 vt1 vt2 vt3 x5sp x16imm
01001100100xxxxx0010xxxxxxxxxxxx st1 memvm x5sp : vmsz vt0 vt1 vt2 vt3 x5sp x16imm
01001100100xxxxx0100xxxxxxxxxxxx st3 memvm x5sp : vmsz vt0 vt1 vt2 x5sp x16imm
01001100100xxxxx0110xxxxxxxxxxxx st1 memvm x5sp : vmsz vt0 vt1 vt2 x5sp x16imm
01001100100xxxxx0111xxxxxxxxxxxx st1 memvm x5sp : vmsz vt0 x5sp x16imm
01001100100xxxxx1000xxxxxxxxxxxx st2 memvm x5sp : vmsz vt0 vt1 x5sp x16imm
01001100100xxxxx1010xxxxxxxxxxxx st1 memvm x5sp : vmsz vt0 vt1 x5sp x16imm

01001100110xxxxx0000xxxxxxxxxxxx ld4 vt0 vt1 vt2 vt3 x5sp : memvm vmsz x5sp x16imm
01001100110xxxxx0010xxxxxxxxxxxx ld1 vt0 vt1 vt2 vt3 x5sp : memvm vmsz x5sp x16imm
01001100110xxxxx0100xxxxxxxxxxxx ld3 vt0 vt1 vt2 x5sp : memvm vmsz x5sp x16imm
01001100110xxxxx0110xxxxxxxxxxxx ld1 vt0 vt1 vt2 x5sp : memvm vmsz x5sp x16imm
01001100110xxxxx0111xxxxxxxxxxxx ld1 vt0 x5sp : memvm vmsz x5sp x16imm
01001100110xxxxx1000xxxxxxxxxxxx ld2 vt0 vt1 x5sp : memvm vmsz x5sp x16imm
01001100110xxxxx1010xxxxxxxxxxxx ld1 vt0 vt1 x5sp : memvm vmsz x5sp x16imm

## Advanced SIMD load/store single structure

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