i#2626 AArch64 encoder: Add support for fmov from GPR to FPR. #3008
Conversation
This commit adds encoder/decoder support for fmov from GPRs to FPRs. It does not add support for the variant to move a 64 bit GPR to the top of a 128 bit register (FMOV <Vd>.D[1], <Xn>). I think for that variant, we would need a way to express the top half of a 128 bit register. Issue #2626 Change-Id: I9105b5ce5cc38a6b6cd33c8390a8822b091a44cf
|
I plan to follow this change up with another one implementing |
Change-Id: I15afa813985bd771ad5af18b78d68d294b7f5003
core/arch/aarch64/instr_create.h
Outdated
| @@ -575,6 +575,15 @@ | |||
| #define INSTR_CREATE_sub_shimm(dc, rd, rn, rm_or_imm, sht, sha) \ | |||
| INSTR_CREATE_sub_shift(dc, rd, rn, rm_or_imm, sht, sha) | |||
|
|
|||
| /** | |||
| * Creates a FMOV instruction to move between GPRs and floating point registers. | |||
core/arch/aarch64/instr_create.h
Outdated
| /** | ||
| * Creates a FMOV instruction to move between GPRs and floating point registers. | ||
| * \param dc The void * dcontext used to allocate memory for the instr_t. | ||
| * \param Rd The output register. |
There was a problem hiding this comment.
nit: extra spaces here and on the next line
Note that for x86 we do not identify which bits are used within SIMD registers: there are so many patterns we just have "N bits out of 128" without specifying which N and it is up to tools to dispatch on opcode if it matters. |
Change-Id: I599803d8434b9b19e2606fd9b5b4dea997a0e195
Right, this works for FMOV, as the 128 bit register argument is not ambiguous |
This commit adds encoder/decoder support for fmov from GPRs to FPRs.
It does not add support for the variant to move a 64 bit GPR to the top
of a 128 bit register (
FMOV <Vd>.D[1], <Xn>). I think for that variant,we would need a way to express the top half of a 128 bit register.
Issue #2626