i#3544 riscv64, part 1: add instruction codec #5666
Merged
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
Add the main source file for instruction codec whose goal is to decode and encode all RISC-V instructions. At the moment only the decoding part is implemented. The decoding process is based on instr_info_t structures and is separated into two stages: 1. Instruction opcode decoding to retrieve a corresponding rv_instr_info_t. This gives the codec information on the number and type of source and destination operands. 2. Instruction operand decoding. All operands are decodec utilizing the data from instr_info_t and a set of operand decoder functions gathered in the opnd_decoders array indexed by the operand field type. Note: The codec.c file is not yet added to the build system as it relies on a set of generated files with opcode and instr_info_t data. The script for that as well as Instruction Set Listing files will follow in later commits. Note 2: There is currently no support for decoding of translated instructions and hence orig_pc is never used. In fact all base+disp operands utilize opnd_create_mem_instr() which id described as a PC-relative memory reference, so it "should" be resistant to the change in base address. Issue #3544 Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
|
Note to self. The error reported in ci-clang-format run is: Though at the beginning of the log (line 16) I see # error RISC-V codec only supports 64-bit architectures (mask+match -> code).So that is definitely not a "function name". I'll change the line though. |
Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
FYI, this is from vera++ which apparently does not recognize preprocessor lines? If you wanted to try to tweak the checker instead -- easier to make the change you already made though. |
- Use GET_FIELD() where possible. - Use TESTALL() for bit tests. - Use BUFFER_SIZE_ELEMENTS() instead of ARRAY_SIZE(). - Rename rv_instr_info_t::nfo -> rv_instr_info_t::info. - Add layout comments to fields decoders and format enums. - Remove doxygen comment headers from the internal code. - Fix spelling. - Use opnd_create_pc() for decoding PC-relative branch targets. Signed-off-by: Stanislaw Kardach <kda@semihalf.com>
|
run arm tests |
|
Sorry for pressing the "update branch" button by mistake. Unfortunate result of a trackpad miss-click. |
derekbruening
approved these changes
Oct 7, 2022
semihalf-kardach-stanislaw
deleted the
i3544-riscv64-p1-add-instr-codec
branch
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Add the main source file for instruction codec whose goal is to decode and encode all RISC-V instructions. At the moment only the decoding part is implemented.
The decoding process is based on instr_info_t structures and is separated into two stages:
Note:
The codec.c file is not yet added to the build system as it relies on a set of generated files with opcode and instr_info_t data. The script for that as well as Instruction Set Listing files will follow in later commits.
Note 2:
There is currently no support for decoding of translated instructions and hence orig_pc is never used. In fact all base+disp operands utilize opnd_create_mem_instr() which is described as a PC-relative memory reference, so it "should" be resistant to the change in base address.
Issue #3544
Signed-off-by: Stanislaw Kardach kda@semihalf.com