This work was done for EEE6225 System Design module @ University of Sheffield 2015-2016 by Group 1
Group members: Rael Sasiak-Rushby, Matthew Fergusson, Ben Trevett and Dominic LeBlanc
It's our low area implementation of the AES on FPGA. I, with permission of the rest of the group, have uploaded the project. Why? because when we were coding there wasn't much help out there besides research papers, which didn't include any VHDL.
This project achieved the criteria for the module, coming in at 456 slices and processing ~37.7Mbps. Full details can be found in the Final report document.
I'm not going to pretend I know the full copyright legalities of this, but I will warn future students that obviously you can't just copy this project. It will get noticed by plaigarism detection software... Please feel free to use this as reference material for any VHDL projects you may have.
Our submitted report on the matter can be found in the AES Final Report.pdf. Here you can find details of the design and how we achieved the low area criteria. It's only 5 pages, so it's definitely worth a read.