[WIP] Porting corev support

rtos/pulpos/common/include/pos/implem/irq.h

@@ -115,9 +115,9 @@ static inline unsigned int pos_irq_get_fc_vector_base()
 #if defined(__RISCV_GENERIC__)
         return hal_spr_read(0x305) & ~1;
 #elif defined(ARCHI_CORE_HAS_SECURITY) && !defined(ARCHI_CORE_HAS_1_10)
-        return __builtin_pulp_spr_read(SR_MTVEC);
+        return __SPRREAD(SR_MTVEC);
 #elif defined(ARCHI_CORE_HAS_1_10)
-        return __builtin_pulp_spr_read(SR_MTVEC) & ~1;
+        return __SPRREAD(SR_MTVEC) & ~1;
 #elif defined(APB_SOC_VERSION) && APB_SOC_VERSION >= 2
         return apb_soc_ctrl_fc_boot_get(ARCHI_APB_SOC_CTRL_ADDR);
 #endif
@@ -143,9 +143,9 @@ static inline void pos_irq_set_fc_vector_base(unsigned int base)
 #if defined(__RISCV_GENERIC__)
         hal_spr_write(0x305, base);
 #elif defined(ARCHI_CORE_HAS_SECURITY) && !defined(ARCHI_CORE_HAS_1_10)
-        __builtin_pulp_spr_write(SR_MTVEC, base);
+        __SPRWRITE(SR_MTVEC, base);
 #elif defined(ARCHI_CORE_HAS_1_10)
-        __builtin_pulp_spr_write(SR_MTVEC, base | 1);
+        __SPRWRITE(SR_MTVEC, base | 1);
 #elif defined(APB_SOC_VERSION) && APB_SOC_VERSION >= 2
         apb_soc_ctrl_fc_boot_set(ARCHI_APB_SOC_CTRL_ADDR, base);
 #endif

rtos/pulpos/common/kernel/crt0.S

@@ -21,6 +21,9 @@
 #include "archi/pulp.h"
 
     .section .text_l2
+#ifdef ARCHI_HAS_COREV
+    .attribute arch, "rv32imc_zicsr_xcv"
+#endif
     .global pos_init_entry
 pos_init_entry:
 

rtos/pulpos/common/kernel/irq_asm.S

@@ -20,7 +20,9 @@
 
 
   .section .text_l2
-
+#ifdef ARCHI_HAS_COREV
+  .attribute arch, "rv32imc_xcv"
+#endif
   .global pos_irq_call_external_c_function
 pos_irq_call_external_c_function:
 

rtos/pulpos/common/kernel/soc_event_eu.S

@@ -21,7 +21,9 @@
 #include <archi/pulp.h>
 
     .section .text_l2
-
+#ifdef ARCHI_HAS_COREV
+    .attribute arch, "rv32imc_xcv"
+#endif
 
     #
     # SOC event handler entry
@@ -59,7 +61,11 @@ pos_soc_event_handler_asm:
     sw  x9, 0(x10)
 
     # Extract ID part
+#ifdef ARCHI_HAS_COREV
+    cv.extractur x10, x8, EU_SOC_EVENTS_EVENT_MASK_BITS-1, EU_SOC_EVENTS_EVENT_MASK_OFFSET
+#else
     p.extractu x10, x8, EU_SOC_EVENTS_EVENT_MASK_BITS-1, EU_SOC_EVENTS_EVENT_MASK_OFFSET
+#endif
 
 
 
@@ -135,7 +141,11 @@ pos_soc_event_store_asm:
     lw      x12, %tiny(pos_soc_event_status)(x11)
     andi    x10, x10, 0x1f
 
+#ifdef ARCHI_HAS_COREV
+    cv.bsetr x12, x12, x10
+#else
     p.bsetr x12, x12, x10
+#endif
 
     sw      x12, %tiny(pos_soc_event_status)(x11)
 

rtos/pulpos/common/kernel/soc_event_v2_itc.S

@@ -22,7 +22,9 @@
 
 
     .section .text_l2
-
+#ifdef ARCHI_HAS_COREV
+    .attribute arch, "rv32imc_xcv"
+#endif
     #
     # SOC event handler entry
     #
@@ -41,7 +43,6 @@
     sw  x10, 8(sp)
     sw  x11, 12(sp)
     sw  x12, 16(sp)
-    sw  t0, 20(sp)
 
 
 
@@ -74,9 +75,17 @@
     lw   x11, %tiny(pos_soc_event_callback_arg)(x11)
 #else
     la   t0, pos_soc_event_callback
+#ifdef ARCHI_HAS_COREV
+    cv.lw x12, t0(x11)
+#else
     p.lw x12, t0(x11)
+#endif /*ARCHI_HAS_COREV*/
     la   t0, pos_soc_event_callback_arg
+#ifdef ARCHI_HAS_COREV
+    cv.lw x11, t0(x11)
+#else
     p.lw x11, t0(x11)
+#endif /*ARCHI_HAS_COREV*/
 #endif
     la   x9, pos_soc_event_handler_end_asm
     j    pos_irq_call_external_c_function
@@ -101,17 +110,31 @@ pos_soc_event_store_asm:
     lw      x12, %tiny(pos_soc_event_status)(x11)
 #else
     la   t0, pos_soc_event_status
+#ifdef ARCHI_HAS_COREV
+    cv.lw x12, t0(x11)
+#else
     p.lw x12, t0(x11)
+#endif /*ARCHI_HAS_COREV*/
 #endif
     andi    x10, x10, 0x1f
-
+#ifdef ARCHI_HAS_COREV
+    li     x11, 1
+    sll    x11, x11, x10
+    or     x12, x12, x11
+    #cv.bsetr x12, x12, x10    #rD = rs1 | (((1 << (rs2[9:5]+1)) – 1) << rs2[4:0])
+#else
     p.bsetr x12, x12, x10
+#endif /*ARCHI_HAS_COREV*/
 
 #ifdef CONFIG_NO_STD_RELOC
     sw      x12, %tiny(pos_soc_event_status)(x11)
 #else
     la      t0, pos_soc_event_status
+#ifdef ARCHI_HAS_COREV
+    cv.sw    x12, t0(x11)
+#else
     p.sw    x12, t0(x11)
+#endif /*ARCHI_HAS_COREV*/
 #endif
 
 
@@ -126,6 +149,5 @@ pos_soc_event_handler_end_asm:
     lw  x10, 8(sp)
     lw  x11, 12(sp)
     lw  x12, 16(sp)
-    lw  t0, 20(sp)
     add sp, sp, 128
     mret

rtos/pulpos/common/kernel/task_asm.S

@@ -21,7 +21,9 @@
 #include <pos/data/data.h>
 
     .section .text_l2
-
+#ifdef ARCHI_HAS_COREV
+    .attribute arch, "rv32imc_xcv"
+#endif
     .global pos_task_push_asm
 pos_task_push_asm:
 

rtos/pulpos/common/kernel/time_asm.S

@@ -21,7 +21,9 @@
 #include <pos/data/data.h>
 
     .section .text_l2
-
+#ifdef ARCHI_HAS_COREV
+    .attribute arch, "rv32imc_xcv"
+#endif
     .global pos_time_timer_handler_asm
 pos_time_timer_handler_asm:
     add sp, sp, -8

rtos/pulpos/pulp/drivers/cluster/pe-eu-v3.S

@@ -21,7 +21,9 @@
 #include <pos/data/data.h>
 
     .section .cluster.text , "ax"
-
+#ifdef ARCHI_HAS_COREV
+    .attribute arch, "rv32imc_xcv"
+#endif
     .global pos_pe_start
 pos_pe_start:
     csrr    a0, 0xF14
@@ -142,7 +144,12 @@ pos_master_no_slave_barrier:
 
     // Set stack on slaves
     // For that we push first the function for setting stack, then the stack size and the base
+#ifdef ARCHI_HAS_COREV
+    //cv.beqimm t5, 0, pos_master_loop_no_slave
+    beqz    t5, pos_master_loop_no_slave
+#else
     p.beqimm t5, 0, pos_master_loop_no_slave
+#endif
     sw      s10, EU_DISPATCH_DEMUX_OFFSET + EU_DISPATCH_FIFO_ACCESS(s3)
     sw      t2, EU_DISPATCH_DEMUX_OFFSET + EU_DISPATCH_FIFO_ACCESS(s3)
     sw      sp, EU_DISPATCH_DEMUX_OFFSET + EU_DISPATCH_FIFO_ACCESS(s3)
@@ -155,15 +162,35 @@ pos_master_loop_no_slave:
 
 pos_master_sleep:
     sw      s4, EU_CORE_MASK_OR(s3)
+#ifdef ARCHI_HAS_COREV
+    //cv.elw   x0, EU_CORE_EVENT_WAIT_CLEAR(s3)
+    lw         x0, EU_CORE_EVENT_WAIT_CLEAR(s3)
+    //beqz       x0, hal_itc_wait_for_interrupt
+    bnez       x0, L10
+    wfi
+L10:
+
+#else
     p.elw   x0, EU_CORE_EVENT_WAIT_CLEAR(s3)
+#endif
     sw      s4, EU_CORE_MASK_AND(s3)
     j       pos_master_loop
 
 
 
 pos_push_event_to_fc_wait:
     sw      s4, EU_CORE_MASK_OR(s3)
+#ifdef ARCHI_HAS_COREV
+    //cv.elw   x0, EU_CORE_EVENT_WAIT_CLEAR(s3)
+    lw         x0, EU_CORE_EVENT_WAIT_CLEAR(s3)
+    //beqz       x0, hal_itc_wait_for_interrupt
+    bnez       x0, L11
+    wfi
+L11:
+
+#else
     p.elw   x0, EU_CORE_EVENT_WAIT_CLEAR(s3)
+#endif
     sw      s4, EU_CORE_MASK_AND(s3)
     j       pos_push_event_to_fc_retry
 
@@ -182,11 +209,6 @@ pos_push_event_to_fc_wait:
 
 
 
-
-
-
-
-
 
 
 
@@ -210,16 +232,50 @@ pos_fork_return:
 #ifdef ARCHI_HAS_CC
     // When the cluster has a controller barrier 0 is used for normal team barrier
     // and barrier 1 is used for end of offload
+#ifdef ARCHI_HAS_COREV
+    //cv.elw   t0, EU_BARRIER_DEMUX_OFFSET + EU_HW_BARR_TRIGGER_WAIT_CLEAR + EU_BARRIER_SIZE(s2)
+    lw         t0, EU_BARRIER_DEMUX_OFFSET + EU_HW_BARR_TRIGGER_WAIT_CLEAR + EU_BARRIER_SIZE(s2)
+    //beqz       t0, hal_itc_wait_for_interrupt
+    bnez       t0, L0
+    wfi
+L0:
+#else
     p.elw   t0, EU_BARRIER_DEMUX_OFFSET + EU_HW_BARR_TRIGGER_WAIT_CLEAR + EU_BARRIER_SIZE(s2)
+#endif /*ARCHI_HAS_COREV*/
+#else
+#ifdef ARCHI_HAS_COREV
+    //cv.elw   t0, EU_BARRIER_DEMUX_OFFSET + EU_HW_BARR_TRIGGER_WAIT_CLEAR(s2)
+    lw         t0, EU_BARRIER_DEMUX_OFFSET + EU_HW_BARR_TRIGGER_WAIT_CLEAR(s2)
+    //beqz       t0, hal_itc_wait_for_interrupt
+    bnez       t0, L1
+    wfi
+L1:
 #else
     p.elw   t0, EU_BARRIER_DEMUX_OFFSET + EU_HW_BARR_TRIGGER_WAIT_CLEAR(s2)
+#endif /*ARCHI_HAS_COREV*/
 #endif    
 
 pos_wait_for_dispatch:
 
     // Wait for PC + arg information from dispatcher
+#ifdef ARCHI_HAS_COREV
+    //cv.elw   t0, EU_DISPATCH_DEMUX_OFFSET + EU_DISPATCH_FIFO_ACCESS(s2)
+    //cv.elw   a0, EU_DISPATCH_DEMUX_OFFSET + EU_DISPATCH_FIFO_ACCESS(s2)
+    lw   t0, EU_DISPATCH_DEMUX_OFFSET + EU_DISPATCH_FIFO_ACCESS(s2)
+    //beqz t0, hal_itc_wait_for_interrupt
+    bnez       t0, L2
+    wfi
+L2:
+
+    lw   a0, EU_DISPATCH_DEMUX_OFFSET + EU_DISPATCH_FIFO_ACCESS(s2)
+    //beqz a0, hal_itc_wait_for_interrupt
+    bnez       a0, L3
+    wfi
+L3:
+#else
     p.elw   t0, EU_DISPATCH_DEMUX_OFFSET + EU_DISPATCH_FIFO_ACCESS(s2)
     p.elw   a0, EU_DISPATCH_DEMUX_OFFSET + EU_DISPATCH_FIFO_ACCESS(s2)
+#endif
 
     // Check if this is an entry with a barrier at the end (fork entry)
     andi    t1, t0, 1
@@ -243,15 +299,30 @@ pos_other_entry:
 pos_set_slave_stack:
 
     // Multiply the stack size by the core ID and add the stack base to get our stack
+#ifdef ARCHI_HAS_COREV
+    //cv.elw   t0, EU_DISPATCH_DEMUX_OFFSET + EU_DISPATCH_FIFO_ACCESS(s2)
+    lw   t0, EU_DISPATCH_DEMUX_OFFSET + EU_DISPATCH_FIFO_ACCESS(s2)
+//    beqz t0, hal_itc_wait_for_interrupt
+    bnez       t0, L4
+    wfi
+L4:
+
+
+#else
     p.elw   t0, EU_DISPATCH_DEMUX_OFFSET + EU_DISPATCH_FIFO_ACCESS(s2)
+#endif
 #if defined(CONFIG_PULP)
     addi     t5, s3, 0
 #else
     // If the cluster has a cluster controller, the first slave has core ID 0
     // and thus we need to take the next stack
     addi     t5, s3, 1
 #endif
-    mul   t4, t5, a0
+#ifdef ARCHI_HAS_COREV
+    cv.muls   t4, t5, a0
+#else
+    p.mul   t4, t5, a0
+#endif
     add     sp, t4, t0
 
     ret

rtos/pulpos/pulp/include/pos/chips/pulp/config.h

@@ -29,7 +29,6 @@
 #define CONFIG_PULP 1
 #define PULP_CHIP_STR pulp
 #define PULP_CHIP_FAMILY_STR pulp
-#define ARCHI_CORE_HAS_PULPV2 1
 
 #define ARCHI_CORE_HAS_1_10 1
 

rtos/pulpos/pulp/rules/pulpos/targets/pulp.mk

@@ -12,13 +12,15 @@ CHIP_CORE_ISA = pulpv2
 endif
 
 ifeq '$(CHIP_CORE_ISA)' 'corev'
-ISA_SPEC = rv32imfc_xcv
+PULP_CFLAGS += -DARCHI_HAS_COREV -DPLP_NO_BUILTIN
+ISA_SPEC = rv32imf_xcv
 ADDITIONAL_SPEC= 
 PULP_CC = riscv32-corev-elf-gcc 
 PULP_AR ?= riscv32-corev-elf-ar
 PULP_LD ?= riscv32-corev-elf-gcc
 PULP_OBJDUMP ?= riscv32-corev-elf-objdump
 else
+PULP_CFLAGS += -DARCHI_CORE_HAS_PULPV2
 PULP_CC = riscv32-unknown-elf-gcc 
 PULP_AR ?= riscv32-unknown-elf-ar
 PULP_LD ?= riscv32-unknown-elf-gcc

rtos/pulpos/pulp_archi/include/archi/gap_utils.h

@@ -22,18 +22,22 @@ static inline unsigned int __attribute__ ((always_inline)) ExtInsMaskFast_archi(
 static inline unsigned int __attribute__ ((always_inline)) ExtInsMaskSafe_archi(unsigned int Size, unsigned int Offset) { return ((((Size-1)&0x1F)<<5)|(Offset&0x1F)); }
 
 #if defined(__riscv__) && !defined(RV_ISA_RV32)
+#if !defined(PLP_NO_BUILTIN)
 #define GAP_WRITE_VOL(base, offset, value) __builtin_pulp_write_base_off_v((value), (base), (offset))
-#define GAP_WRITE(base, offset, value)     __builtin_pulp_OffsetedWrite((value), (int *)(base), (offset))
-#define GAP_READ(base, offset)             __builtin_pulp_OffsetedRead((int *)(base), (offset))
+#else
+#define GAP_WRITE_VOL(base, offset, value) archi_write32((base) + (offset), (value))
+#endif
+#define GAP_WRITE(base, offset, value)     __WRITE_BASE_OFF_VOL((value), (int *)(base), (offset))
+#define GAP_READ(base, offset)             __READ_BASE_OFF_VOL((int *)(base), (offset))
 #else
 #define GAP_WRITE_VOL(base, offset, value) archi_write32((base) + (offset), (value))
 #define GAP_WRITE(base, offset, value)     archi_write32((base) + (offset), (value))
 #define GAP_READ(base, offset)             archi_read32((base) + (offset))
 #endif
 
-#define GAP_BINSERT(dst,src,size,off)  __builtin_pulp_binsert((dst), ~(((1UL<<(size))-1)<<(off)), (src), (((1UL<<(size))-1)<<(off)), (off))
-#define GAP_BINSERT_R(dst,src,size,off)  __builtin_pulp_binsert_r((dst), (src), ExtInsMaskFast_archi((size), (off)))
-#define GAP_BEXTRACTU(src,size,off)    __builtin_pulp_bextractu((src), (size), (off))
-#define GAP_BEXTRACT(src,size,off)     __builtin_pulp_bextract((src), (size), (off))
+#define GAP_BINSERT(dst,src,size,off)  __BITINSERT(dst, src, size, off)
+#define GAP_BINSERT_R(dst,src,size,off)  __BITINSERT_R(dst, src, size, off)
+#define GAP_BEXTRACTU(src,size,off)    __BITEXTRACTU(src, size, off)
+#define GAP_BEXTRACT(src,size,off)     __BITEXTRACT(src, size, off)
 
 #endif