- Create a project named
aes_engine
in Vivado 2018.3 using the board ZedBoard Zynq Evaluation and Development Kit (xc7z020clg484-1). - Initialize a git repository in the
aes_engine.srcs
directory. - Set the remote to the project repo.
- Checkout to a new branch with the relevant module name as the branch name. Refer to the 1st point of the Module Conventions.
- All AES step modules will have no capitalization, spaces and non-alphabetical characters. The results are given below:
- KeyExpansion:
keyexpansion
- S-Box:
sbox
- SubBytes:
subbytes
- ShiftRows:
shiftrows
- MixColumns:
mixcolumns
- AddRoundKey:
addroundkey
- KeyExpansion:
- All module I/O specifications are to follow the following:
- If applicable, the block state is to be the first input with the name
state
. - If applicable, the user key is to be second input after
state
(first if it doesn't exist) with the namekey
. - If applicable, the clock and reset signals are to be the last input with the names
clk
andrst
in given order. - If applicable, the start input signal will be named
start
and be placed beforeclk
if it exists. - If applciable, the end output signal will be named
end
and be the first output.
- If applicable, the block state is to be the first input with the name
- All testbenches are to use the following additional rules:
- Test modules are to be named
test_[MODULENAME]
where[MODULENAME]
is the step module being tested. - Test modules are to not have any I/O.
- Test modules are to be named
- Because of the project requirements, the higher level module is exempt from these conventions except the testbench convention.
This repository is licensed under BSD-3-Clause. Refer to LICENSE.md for more details.