Skip to content

Commit

Permalink
Merge pull request #10 from torvalds/master
Browse files Browse the repository at this point in the history
Auto Fork - Updates from base
  • Loading branch information
Esteban-Rocha authored Jan 23, 2018
2 parents acb8aa2 + a84a8ab commit 0141d30
Show file tree
Hide file tree
Showing 147 changed files with 1,689 additions and 539 deletions.
46 changes: 46 additions & 0 deletions Documentation/virtual/kvm/api.txt
Original file line number Diff line number Diff line change
Expand Up @@ -3403,6 +3403,52 @@ invalid, if invalid pages are written to (e.g. after the end of memory)
or if no page table is present for the addresses (e.g. when using
hugepages).

4.108 KVM_PPC_GET_CPU_CHAR

Capability: KVM_CAP_PPC_GET_CPU_CHAR
Architectures: powerpc
Type: vm ioctl
Parameters: struct kvm_ppc_cpu_char (out)
Returns: 0 on successful completion
-EFAULT if struct kvm_ppc_cpu_char cannot be written

This ioctl gives userspace information about certain characteristics
of the CPU relating to speculative execution of instructions and
possible information leakage resulting from speculative execution (see
CVE-2017-5715, CVE-2017-5753 and CVE-2017-5754). The information is
returned in struct kvm_ppc_cpu_char, which looks like this:

struct kvm_ppc_cpu_char {
__u64 character; /* characteristics of the CPU */
__u64 behaviour; /* recommended software behaviour */
__u64 character_mask; /* valid bits in character */
__u64 behaviour_mask; /* valid bits in behaviour */
};

For extensibility, the character_mask and behaviour_mask fields
indicate which bits of character and behaviour have been filled in by
the kernel. If the set of defined bits is extended in future then
userspace will be able to tell whether it is running on a kernel that
knows about the new bits.

The character field describes attributes of the CPU which can help
with preventing inadvertent information disclosure - specifically,
whether there is an instruction to flash-invalidate the L1 data cache
(ori 30,30,0 or mtspr SPRN_TRIG2,rN), whether the L1 data cache is set
to a mode where entries can only be used by the thread that created
them, whether the bcctr[l] instruction prevents speculation, and
whether a speculation barrier instruction (ori 31,31,0) is provided.

The behaviour field describes actions that software should take to
prevent inadvertent information disclosure, and thus describes which
vulnerabilities the hardware is subject to; specifically whether the
L1 data cache should be flushed when returning to user mode from the
kernel, and whether a speculation barrier should be placed between an
array bounds check and the array access.

These fields use the same bit definitions as the new
H_GET_CPU_CHARACTERISTICS hypercall.

5. The kvm_run structure
------------------------

Expand Down
2 changes: 1 addition & 1 deletion Documentation/x86/pti.txt
Original file line number Diff line number Diff line change
Expand Up @@ -78,7 +78,7 @@ this protection comes at a cost:
non-PTI SYSCALL entry code, so requires mapping fewer
things into the userspace page tables. The downside is
that stacks must be switched at entry time.
d. Global pages are disabled for all kernel structures not
c. Global pages are disabled for all kernel structures not
mapped into both kernel and userspace page tables. This
feature of the MMU allows different processes to share TLB
entries mapping the kernel. Losing the feature means more
Expand Down
1 change: 1 addition & 0 deletions MAINTAINERS
Original file line number Diff line number Diff line change
Expand Up @@ -9085,6 +9085,7 @@ F: drivers/usb/image/microtek.*

MIPS
M: Ralf Baechle <ralf@linux-mips.org>
M: James Hogan <jhogan@kernel.org>
L: linux-mips@linux-mips.org
W: http://www.linux-mips.org/
T: git git://git.linux-mips.org/pub/scm/ralf/linux.git
Expand Down
2 changes: 1 addition & 1 deletion Makefile
Original file line number Diff line number Diff line change
Expand Up @@ -2,7 +2,7 @@
VERSION = 4
PATCHLEVEL = 15
SUBLEVEL = 0
EXTRAVERSION = -rc8
EXTRAVERSION = -rc9
NAME = Fearless Coyote

# *DOCUMENTATION*
Expand Down
35 changes: 29 additions & 6 deletions arch/alpha/kernel/sys_sio.c
Original file line number Diff line number Diff line change
Expand Up @@ -102,6 +102,15 @@ sio_pci_route(void)
alpha_mv.sys.sio.route_tab);
}

static bool sio_pci_dev_irq_needs_level(const struct pci_dev *dev)
{
if ((dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) &&
(dev->class >> 8 != PCI_CLASS_BRIDGE_PCMCIA))
return false;

return true;
}

static unsigned int __init
sio_collect_irq_levels(void)
{
Expand All @@ -110,8 +119,7 @@ sio_collect_irq_levels(void)

/* Iterate through the devices, collecting IRQ levels. */
for_each_pci_dev(dev) {
if ((dev->class >> 16 == PCI_BASE_CLASS_BRIDGE) &&
(dev->class >> 8 != PCI_CLASS_BRIDGE_PCMCIA))
if (!sio_pci_dev_irq_needs_level(dev))
continue;

if (dev->irq)
Expand All @@ -120,8 +128,7 @@ sio_collect_irq_levels(void)
return level_bits;
}

static void __init
sio_fixup_irq_levels(unsigned int level_bits)
static void __sio_fixup_irq_levels(unsigned int level_bits, bool reset)
{
unsigned int old_level_bits;

Expand All @@ -139,12 +146,21 @@ sio_fixup_irq_levels(unsigned int level_bits)
*/
old_level_bits = inb(0x4d0) | (inb(0x4d1) << 8);

level_bits |= (old_level_bits & 0x71ff);
if (reset)
old_level_bits &= 0x71ff;

level_bits |= old_level_bits;

outb((level_bits >> 0) & 0xff, 0x4d0);
outb((level_bits >> 8) & 0xff, 0x4d1);
}

static inline void
sio_fixup_irq_levels(unsigned int level_bits)
{
__sio_fixup_irq_levels(level_bits, true);
}

static inline int
noname_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
{
Expand Down Expand Up @@ -181,7 +197,14 @@ noname_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
const long min_idsel = 6, max_idsel = 14, irqs_per_slot = 5;
int irq = COMMON_TABLE_LOOKUP, tmp;
tmp = __kernel_extbl(alpha_mv.sys.sio.route_tab, irq);
return irq >= 0 ? tmp : -1;

irq = irq >= 0 ? tmp : -1;

/* Fixup IRQ level if an actual IRQ mapping is detected */
if (sio_pci_dev_irq_needs_level(dev) && irq >= 0)
__sio_fixup_irq_levels(1 << irq, false);

return irq;
}

static inline int
Expand Down
12 changes: 6 additions & 6 deletions arch/alpha/lib/ev6-memset.S
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@
* The algorithm for the leading and trailing quadwords remains the same,
* however the loop has been unrolled to enable better memory throughput,
* and the code has been replicated for each of the entry points: __memset
* and __memsetw to permit better scheduling to eliminate the stalling
* and __memset16 to permit better scheduling to eliminate the stalling
* encountered during the mask replication.
* A future enhancement might be to put in a byte store loop for really
* small (say < 32 bytes) memset()s. Whether or not that change would be
Expand All @@ -34,7 +34,7 @@
.globl memset
.globl __memset
.globl ___memset
.globl __memsetw
.globl __memset16
.globl __constant_c_memset

.ent ___memset
Expand Down Expand Up @@ -415,9 +415,9 @@ end:
* to mask stalls. Note that entry point names also had to change
*/
.align 5
.ent __memsetw
.ent __memset16

__memsetw:
__memset16:
.frame $30,0,$26,0
.prologue 0

Expand Down Expand Up @@ -596,8 +596,8 @@ end_w:
nop
ret $31,($26),1 # L0 :

.end __memsetw
EXPORT_SYMBOL(__memsetw)
.end __memset16
EXPORT_SYMBOL(__memset16)

memset = ___memset
__memset = ___memset
Expand Down
4 changes: 2 additions & 2 deletions arch/arm/boot/dts/da850-lcdk.dts
Original file line number Diff line number Diff line change
Expand Up @@ -293,12 +293,12 @@
label = "u-boot env";
reg = <0 0x020000>;
};
partition@0x020000 {
partition@20000 {
/* The LCDK defaults to booting from this partition */
label = "u-boot";
reg = <0x020000 0x080000>;
};
partition@0x0a0000 {
partition@a0000 {
label = "free space";
reg = <0x0a0000 0>;
};
Expand Down
10 changes: 8 additions & 2 deletions arch/arm/boot/dts/kirkwood-openblocks_a7.dts
Original file line number Diff line number Diff line change
Expand Up @@ -53,7 +53,8 @@
};

pinctrl: pin-controller@10000 {
pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header>;
pinctrl-0 = <&pmx_dip_switches &pmx_gpio_header
&pmx_gpio_header_gpo>;
pinctrl-names = "default";

pmx_uart0: pmx-uart0 {
Expand Down Expand Up @@ -85,11 +86,16 @@
* ground.
*/
pmx_gpio_header: pmx-gpio-header {
marvell,pins = "mpp17", "mpp7", "mpp29", "mpp28",
marvell,pins = "mpp17", "mpp29", "mpp28",
"mpp35", "mpp34", "mpp40";
marvell,function = "gpio";
};

pmx_gpio_header_gpo: pxm-gpio-header-gpo {
marvell,pins = "mpp7";
marvell,function = "gpo";
};

pmx_gpio_init: pmx-init {
marvell,pins = "mpp38";
marvell,function = "gpio";
Expand Down
2 changes: 1 addition & 1 deletion arch/arm/boot/dts/sun4i-a10.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -1104,7 +1104,7 @@

be1_out_tcon0: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon1_in_be0>;
remote-endpoint = <&tcon0_in_be1>;
};

be1_out_tcon1: endpoint@1 {
Expand Down
2 changes: 1 addition & 1 deletion arch/arm/boot/dts/sun7i-a20.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -1354,7 +1354,7 @@

be1_out_tcon0: endpoint@0 {
reg = <0>;
remote-endpoint = <&tcon1_in_be0>;
remote-endpoint = <&tcon0_in_be1>;
};

be1_out_tcon1: endpoint@1 {
Expand Down
2 changes: 2 additions & 0 deletions arch/arm/configs/sunxi_defconfig
Original file line number Diff line number Diff line change
Expand Up @@ -10,6 +10,7 @@ CONFIG_SMP=y
CONFIG_NR_CPUS=8
CONFIG_AEABI=y
CONFIG_HIGHMEM=y
CONFIG_CMA=y
CONFIG_ARM_APPENDED_DTB=y
CONFIG_ARM_ATAG_DTB_COMPAT=y
CONFIG_CPU_FREQ=y
Expand All @@ -33,6 +34,7 @@ CONFIG_CAN_SUN4I=y
# CONFIG_WIRELESS is not set
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_DMA_CMA=y
CONFIG_BLK_DEV_SD=y
CONFIG_ATA=y
CONFIG_AHCI_SUNXI=y
Expand Down
1 change: 1 addition & 0 deletions arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -66,6 +66,7 @@
<&cpu1>,
<&cpu2>,
<&cpu3>;
interrupt-parent = <&intc>;
};

psci {
Expand Down
13 changes: 8 additions & 5 deletions arch/arm64/boot/dts/marvell/armada-cp110-master.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -63,8 +63,10 @@
cpm_ethernet: ethernet@0 {
compatible = "marvell,armada-7k-pp22";
reg = <0x0 0x100000>, <0x129000 0xb000>;
clocks = <&cpm_clk 1 3>, <&cpm_clk 1 9>, <&cpm_clk 1 5>;
clock-names = "pp_clk", "gop_clk", "mg_clk";
clocks = <&cpm_clk 1 3>, <&cpm_clk 1 9>,
<&cpm_clk 1 5>, <&cpm_clk 1 18>;
clock-names = "pp_clk", "gop_clk",
"mg_clk","axi_clk";
marvell,system-controller = <&cpm_syscon0>;
status = "disabled";
dma-coherent;
Expand Down Expand Up @@ -155,7 +157,8 @@
#size-cells = <0>;
compatible = "marvell,orion-mdio";
reg = <0x12a200 0x10>;
clocks = <&cpm_clk 1 9>, <&cpm_clk 1 5>;
clocks = <&cpm_clk 1 9>, <&cpm_clk 1 5>,
<&cpm_clk 1 6>, <&cpm_clk 1 18>;
status = "disabled";
};

Expand Down Expand Up @@ -338,8 +341,8 @@
compatible = "marvell,armada-cp110-sdhci";
reg = <0x780000 0x300>;
interrupts = <ICU_GRP_NSR 27 IRQ_TYPE_LEVEL_HIGH>;
clock-names = "core";
clocks = <&cpm_clk 1 4>;
clock-names = "core","axi";
clocks = <&cpm_clk 1 4>, <&cpm_clk 1 18>;
dma-coherent;
status = "disabled";
};
Expand Down
9 changes: 6 additions & 3 deletions arch/arm64/boot/dts/marvell/armada-cp110-slave.dtsi
Original file line number Diff line number Diff line change
Expand Up @@ -63,8 +63,10 @@
cps_ethernet: ethernet@0 {
compatible = "marvell,armada-7k-pp22";
reg = <0x0 0x100000>, <0x129000 0xb000>;
clocks = <&cps_clk 1 3>, <&cps_clk 1 9>, <&cps_clk 1 5>;
clock-names = "pp_clk", "gop_clk", "mg_clk";
clocks = <&cps_clk 1 3>, <&cps_clk 1 9>,
<&cps_clk 1 5>, <&cps_clk 1 18>;
clock-names = "pp_clk", "gop_clk",
"mg_clk", "axi_clk";
marvell,system-controller = <&cps_syscon0>;
status = "disabled";
dma-coherent;
Expand Down Expand Up @@ -155,7 +157,8 @@
#size-cells = <0>;
compatible = "marvell,orion-mdio";
reg = <0x12a200 0x10>;
clocks = <&cps_clk 1 9>, <&cps_clk 1 5>;
clocks = <&cps_clk 1 9>, <&cps_clk 1 5>,
<&cps_clk 1 6>, <&cps_clk 1 18>;
status = "disabled";
};

Expand Down
4 changes: 2 additions & 2 deletions arch/arm64/kvm/handle_exit.c
Original file line number Diff line number Diff line change
Expand Up @@ -45,7 +45,7 @@ static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run)

ret = kvm_psci_call(vcpu);
if (ret < 0) {
kvm_inject_undefined(vcpu);
vcpu_set_reg(vcpu, 0, ~0UL);
return 1;
}

Expand All @@ -54,7 +54,7 @@ static int handle_hvc(struct kvm_vcpu *vcpu, struct kvm_run *run)

static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run)
{
kvm_inject_undefined(vcpu);
vcpu_set_reg(vcpu, 0, ~0UL);
return 1;
}

Expand Down
Loading

0 comments on commit 0141d30

Please sign in to comment.