EttusResearch · turcofran · Jan 24, 2023 · May 24, 2024 · Nov 14, 2025 · Dec 2, 2025
diff --git a/fpga/usrp3/tools/make/viv_design_builder.mak b/fpga/usrp3/tools/make/viv_design_builder.mak
@@ -29,6 +29,7 @@ BUILD_VIVADO_DESIGN = \
 	export VIV_MODE=$(VIVADO_MODE); \
 	export VIV_PROJECT=$(VIVADO_PROJECT); \
 	export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(call uniq,$(DESIGN_SRCS))); \
+	export VIV_OOT_SRCS_FILE=$(OOT_SRCS_FILE); \
 	export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)/../.."; \
 	export VIV_INCR_BUILD=$(INCR_BUILD); \
 	export VIV_SECURE_KEY=$(call RESOLVE_PATH,$(abspath $(SECURE_KEY))); \
@@ -56,6 +57,7 @@ CHECK_VIVADO_DESIGN = \
 	export VIV_PART_NAME=`python3 $(TOOLS_DIR)/scripts/viv_gen_part_id.py $(3)/$(4)`; \
 	export VIV_MODE=$(VIVADO_MODE); \
 	export VIV_DESIGN_SRCS=$(call RESOLVE_PATHS,$(call uniq,$(DESIGN_SRCS))); \
+	export VIV_OOT_SRCS_FILE=$(OOT_SRCS_FILE); \
 	export VIV_VERILOG_DEFS="$(VERILOG_DEFS) UHD_FPGA_DIR=$(BASE_DIR)../../"; \
 	cd $(BUILD_DIR); \
 	$(TOOLS_DIR)/scripts/launch_vivado.py --parse-config $(TOOLS_DIR)/scripts/check_config.json -mode $(VIVADO_MODE) -source $(call RESOLVE_PATH,$(1)) -log build.log -journal $(2).jou

diff --git a/fpga/usrp3/tools/scripts/viv_utils.tcl b/fpga/usrp3/tools/scripts/viv_utils.tcl
@@ -28,6 +28,7 @@ namespace eval ::vivado_utils {
     variable g_part_name    $::env(VIV_PART_NAME)
     variable g_output_dir   $::env(VIV_OUTPUT_DIR)
     variable g_source_files $::env(VIV_DESIGN_SRCS)
+    variable g_oot_srcs_file $::env(VIV_OOT_SRCS_FILE)
     variable g_vivado_mode  $::env(VIV_MODE)
     variable g_project_save $::env(VIV_PROJECT)
     variable g_secure_key   $::env(VIV_SECURE_KEY)
@@ -51,6 +52,7 @@ proc ::vivado_utils::initialize_project { {save_to_disk 0} } {
     variable g_part_name
     variable g_output_dir
     variable g_source_files
+    variable g_oot_srcs_file
     variable g_project_save
 
     variable bd_files ""
@@ -65,6 +67,18 @@ proc ::vivado_utils::initialize_project { {save_to_disk 0} } {
         create_project -in_memory -part $g_part_name
     }
 
+    # Get OOT sources from resources file to avoid ARG_MAX issue
+    if {[info exists g_oot_srcs_file] && [file exists $g_oot_srcs_file]} {
+        puts "BUILDER: Reading sources from $g_oot_srcs_file"
+        set fh [open $g_oot_srcs_file r];
+        while {[gets $fh line] >= 0} {
+            if {$line ne ""} {
+                append g_source_files " " $line
+            }
+        }
+        close $fh
+    }
+
     # Expand directories to include their contents (needed for HLS outputs)
     foreach src_file $g_source_files {
         if [expr [file isdirectory $src_file] == 1] {
@@ -97,7 +111,9 @@ proc ::vivado_utils::initialize_project { {save_to_disk 0} } {
         } elseif [expr [lsearch {.xci} $src_ext] >= 0] {
             puts "BUILDER: Adding IP: $src_file"
             read_ip $src_file
-            set_property generate_synth_checkpoint true [get_files $src_file]
+            if {[catch {set_property generate_synth_checkpoint true [get_files $src_file]} errorstring]} {
+                puts "BUILDER: Failed to set synth checkpoint generation ($errorstring). The process will continue."
+            }
         } elseif [expr [lsearch {.ngc .edif .edf} $src_ext] >= 0] {
             puts "BUILDER: Adding Netlist: $src_file"
             read_edif $src_file

diff --git a/fpga/usrp3/top/e31x/Makefile.e31x.inc b/fpga/usrp3/top/e31x/Makefile.e31x.inc
@@ -90,7 +90,6 @@ $(EXTRAM_SRCS) \
 $(CAP_GEN_GENERIC_SRCS) \
 $(RFNOC_FRAMEWORK_SRCS) \
 $(RFNOC_SRCS) \
-$(RFNOC_OOT_SRCS)\
 $(RFNOC_IMAGE_CORE_SRCS) \
 $(TOP_SRCS) \
 $(MB_XDC) \
@@ -107,6 +106,10 @@ IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(BUILD_DIR)/rfnoc_image_core.vh"
 
 VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_HEADER_DEF) $(RFNOC_IMAGE_CORE_DEFS)
 
+OOT_SRCS_FILE := $(BUILD_DIR)/oot_srcs_$(shell date +%s).f
+$(OOT_SRCS_FILE):
+	@printf "%s\n" $(RFNOC_OOT_SRCS) > $@
+
 # DESIGN_SRCS and VERILOG_DEFS must be defined
 bin: .prereqs
 	@echo "Build directory:: $(BUILD_DIR)"

diff --git a/fpga/usrp3/top/e320/Makefile.e320.inc b/fpga/usrp3/top/e320/Makefile.e320.inc
@@ -108,7 +108,6 @@ $(EXTRAM_SRCS) \
 $(CAP_GEN_GENERIC_SRCS) \
 $(RFNOC_FRAMEWORK_SRCS) \
 $(RFNOC_SRCS) \
-$(RFNOC_OOT_SRCS) \
 $(RFNOC_XPORT_SV_SRCS) \
 $(RFNOC_IMAGE_CORE_SRCS) \
 $(TOP_SRCS) \
@@ -124,8 +123,12 @@ IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(BUILD_DIR)/rfnoc_image_core.vh"
 
 VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_HEADER_DEF) $(RFNOC_IMAGE_CORE_DEFS)
 
+OOT_SRCS_FILE := $(BUILD_DIR)/oot_srcs_$(shell date +%s).f
+$(OOT_SRCS_FILE):
+	@printf "%s\n" $(RFNOC_OOT_SRCS) > $@
+
 # DESIGN_SRCS and VERILOG_DEFS must be defined
-bin: .prereqs
+bin: .prereqs $(OOT_SRCS_FILE)
 	@echo "Build directory:: $(BUILD_DIR)"
 	@echo "Printing MB_XDC:: $(MB_XDC)"
 	@echo "Printing VERILOG_DEFS:: $(VERILOG_DEFS)"

diff --git a/fpga/usrp3/top/n3xx/Makefile.n3xx.inc b/fpga/usrp3/top/n3xx/Makefile.n3xx.inc
@@ -129,7 +129,7 @@ $(TEN_GIGE_PHY_SRCS) $(ONE_GIGE_PHY_SRCS) \
 $(PACKET_PROC_SRCS) $(DSP_SRCS) $(DRAM_SRCS) \
 $(RADIO_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \
 $(RFNOC_FRAMEWORK_SRCS) \
-$(RFNOC_SRCS) $(RFNOC_OOT_SRCS) $(LIB_IP_XCI_SRCS) $(LIB_HLS_IP_SRCS) \
+$(RFNOC_SRCS) $(LIB_IP_XCI_SRCS) $(LIB_HLS_IP_SRCS) \
 $(WHITE_RABBIT_SRCS) \
 $(RFNOC_XPORT_SV_SRCS) \
 $(RFNOC_IMAGE_CORE_SRCS) \
@@ -147,8 +147,12 @@ IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(BUILD_DIR)/rfnoc_image_core.vh"
 
 VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_HEADER_DEF) $(RFNOC_IMAGE_CORE_DEFS)
 
+OOT_SRCS_FILE := $(BUILD_DIR)/oot_srcs_$(shell date +%s).f
+$(OOT_SRCS_FILE):
+	@printf "%s\n" $(RFNOC_OOT_SRCS) > $@
+
 # DESIGN_SRCS and VERILOG_DEFS must be defined
-bin: .prereqs
+bin: .prereqs $(OOT_SRCS_FILE)
 	@echo "Build directory:: $(BUILD_DIR)"
 	@echo "Printing MB_XDC:: $(MB_XDC)"
 	@echo "Printing VERILOG_DEFS:: $(VERILOG_DEFS)"

diff --git a/fpga/usrp3/top/x300/Makefile.x300.inc b/fpga/usrp3/top/x300/Makefile.x300.inc
@@ -104,7 +104,7 @@ $(IOPORT2_SRCS) \
 $(PACKET_PROC_SRCS) $(DSP_SRCS) \
 $(AXI_SRCS) $(AXI4S_SV_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \
 $(LIB_IP_XCI_SRCS) \
-$(RFNOC_FRAMEWORK_SRCS) $(RFNOC_SRCS) $(RFNOC_OOT_SRCS) \
+$(RFNOC_FRAMEWORK_SRCS) $(RFNOC_SRCS) \
 $(RFNOC_XPORT_SV_SRCS) \
 $(RFNOC_IMAGE_CORE_SRCS) \
 $(TOP_SRCS) $(SFP_SERDES_SRCS) $(DRAM_SRCS) \
@@ -121,8 +121,12 @@ IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(BUILD_DIR)/rfnoc_image_core.vh"
 
 VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_HEADER_DEF) $(RFNOC_IMAGE_CORE_DEFS)
 
+OOT_SRCS_FILE := $(BUILD_DIR)/oot_srcs_$(shell date +%s).f
+$(OOT_SRCS_FILE):
+	@printf "%s\n" $(RFNOC_OOT_SRCS) > $@
+
 # DESIGN_SRCS and VERILOG_DEFS must be defined
-bin: .prereqs
+bin: .prereqs $(OOT_SRCS_FILE)
 	@echo "Build directory:: $(BUILD_DIR)"
 	@echo "Printing MB_XDC:: $(MB_XDC)"
 	@echo "Printing VERILOG_DEFS:: $(VERILOG_DEFS)"

diff --git a/fpga/usrp3/top/x400/Makefile.x4xx.inc b/fpga/usrp3/top/x400/Makefile.x4xx.inc
@@ -154,7 +154,7 @@ $(XGE_PCS_PMA_SRCS) \
 $(PACKET_PROC_SRCS) $(VITA_SRCS) $(DSP_SRCS) $(DRAM_SRCS) \
 $(RADIO_SRCS) $(CAP_GEN_GENERIC_SRCS) $(IP_XCI_SRCS) $(BD_SRCS) \
 $(LIB_IP_XCI_SRCS) $(LIB_HLS_IP_SRCS) $(LIBCOREGEN_SRCS) $(WB_SPI_SRCS) \
-$(RFNOC_FRAMEWORK_SRCS) $(RFNOC_SRCS) $(RFNOC_OOT_SRCS) \
+$(RFNOC_FRAMEWORK_SRCS) $(RFNOC_SRCS) \
 $(RFNOC_XPORT_SV_SRCS) $(RFNOC_IMAGE_CORE_SRCS) \
 $(DB_COMMON_SRCS) $(TOP_SRCS) \
 )
@@ -170,11 +170,15 @@ IMAGE_CORE_HEADER_DEF="RFNOC_IMAGE_CORE_HDR=$(BUILD_DIR)/rfnoc_image_core.vh"
 
 VERILOG_DEFS=$(EXTRA_DEFS) $(CUSTOM_DEFS) $(GIT_HASH_VERILOG_DEF) $(IMAGE_CORE_HEADER_DEF) $(RFNOC_IMAGE_CORE_DEFS)
 
+OOT_SRCS_FILE := $(BUILD_DIR)/oot_srcs_$(shell date +%s).f
+$(OOT_SRCS_FILE):
+	@printf "%s\n" $(RFNOC_OOT_SRCS) > $@
+
 show-var:
 	@echo "IP_BUILD_DIR: $(IP_BUILD_DIR)"
 
 # DESIGN_SRCS and VERILOG_DEFS must be defined
-bin: .prereqs
+bin: .prereqs $(OOT_SRCS_FILE)
 	@echo "Build directory:: $(BUILD_DIR)"
 	@echo "Printing MB_XDC:: $(MB_XDC)"
 	@echo "Printing VERILOG_DEFS:: $(VERILOG_DEFS)"

diff --git a/host/cmake/Modules/create_newmod.yml b/host/cmake/Modules/create_newmod.yml
@@ -26,6 +26,8 @@ steps:
     glob: "**/*gain*"
     pattern: gain
     repl: newmod
+- run_subprocess:
+    cmd: ["chmod","-R","u+w","."]
 - comment_out:
     file: apps/CMakeLists.txt
     range: [7, -1]

diff --git a/host/include/uhd/rfnoc/core/rfnoc_imagebuilder_args.json b/host/include/uhd/rfnoc/core/rfnoc_imagebuilder_args.json
@@ -21,7 +21,8 @@
                               "items": { "$ref": "#/definitions/connection" } },
         "connections":      { "type": "array",
                               "items": { "$ref": "#/definitions/connection" } },
-        "secure_image_core":{ "$ref": "#/definitions/secure_image_core" }
+        "secure_image_core":{ "$ref": "#/definitions/secure_image_core" },
+        "user_clocks":      { "$ref": "#/definitions/user_clocks" }
     },
     "required":             ["schema",
                              "chdr_width",
@@ -133,7 +134,24 @@
             "properties": {
                 "noc_blocks":       { "$ref": "#/definitions/noc_blocks" }
             }
-        }
+        },
 
+        "user_clocks": {
+            "type": "object",
+            "patternProperties": {
+                ".*": { "$ref": "#/definitions/user_clock" }
+            }
+        },
+
+        "user_clock": {
+            "type": "object",
+            "properties": {
+                "ip": { "type": "string"},
+                "port_in": { "type": "string"},
+                "port_out": { "type": "string"}
+            },
+            "required": ["ip","port_in","port_out"],
+            "additionalProperties": false
+        }        
     }
 }
diff --git a/host/python/uhd/rfnoc_utils/builder_config.py b/host/python/uhd/rfnoc_utils/builder_config.py
@@ -49,6 +49,7 @@ def __init__(self, config, known_modules, device, include_paths):
         self.clk_domains = []
         self.resets = []
         self.block_ports = {}
+        self.user_clocks = {}
         self.clocks = {}
         self.log = logging.getLogger(__name__)
         self.warnings = []
@@ -825,6 +826,11 @@ def register_clk_index(clock_id, clock_info):
                     clock["direction"] = "in"
                 if clock["direction"] == "out":
                     clock["index"] = register_clk_index(name + "." + clock["name"], clock)
+        # Add user clocks
+        for name, clock in self.user_clocks.items():
+            self.clocks[name + '.' + clock['port_in']] = {"freq": '[]', "name": clock['port_in'], "direction":'in'} # Only port for inputs since the wire blkname_clockname
+            self.clocks[name + '.' + clock['port_out']] = {"freq": '[]', "name": name+'_'+clock['port_out'], "direction":'out'}
+
 
     def _check_clk_domains(self):
         """Check/sanitize clock domain connections.
@@ -835,6 +841,11 @@ def _check_clk_domains(self):
         """
         # Check the given clock connections are valid
         for clk_domain in self.clk_domains:
+            if (
+                clk_domain["srcblk"] in self.user_clocks
+                or clk_domain["dstblk"] in self.user_clocks
+            ):
+                continue
             srcblk = self.get_module(clk_domain["srcblk"])
             dstblk = self.get_module(clk_domain["dstblk"])
             if not srcblk:

diff --git a/host/python/uhd/rfnoc_utils/templates/modules/user_clocks.v.mako b/host/python/uhd/rfnoc_utils/templates/modules/user_clocks.v.mako
@@ -0,0 +1,17 @@
+<%page args="user_clocks"/>\
+\
+%for i, clock in enumerate(user_clocks):
+<%
+  uc_name = clock
+  ip_name = user_clocks[clock]["ip"]
+  port_in = user_clocks[clock]["port_in"]
+  port_out = user_clocks[clock]["port_out"]
+%>\
+wire ${uc_name}_${port_in}_clk;
+  wire ${uc_name}_${port_out}_clk;
+
+  ${ip_name} #() ${uc_name} (
+    .${port_out}(${uc_name}_${port_out}_clk),
+    .${port_in}(${uc_name}_${port_in}_clk)
+  );
+%endfor
diff --git a/host/python/uhd/rfnoc_utils/templates/rfnoc_image_core.sv.mako b/host/python/uhd/rfnoc_utils/templates/rfnoc_image_core.sv.mako
@@ -298,6 +298,10 @@ module rfnoc_image_core #(
   args="connections=io_con, config=config"
 />\
 
+  //---------------------------------------------------------------------------
+  // User Clocks
+  //---------------------------------------------------------------------------
+<%include file="/modules/user_clocks.v.mako" args="user_clocks=config.user_clocks"/>\
 
   //---------------------------------------------------------------------------
   // Clock Domains and Resets