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Juan Gonzalez-Gomez edited this page Nov 2, 2023 · 213 revisions

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Introduction

In this collection you will find Flip Flops. Use these blocks in your digital circuits for opensource FPGAs created with icestudio

Installation in Icestudio

Find information about collections and how to install them on this link: Installing the iceK collection in Icestudio. It was written for the iceK collection as an example. Use the repo of the iceFF collection instead

Quick Download:

  • Download the ZIP file from the latest release
  • ...or get the ZIP file with the latest changes from the main branch: iceFF.zip

D Flip-Flops

The D Flip-Flops store 1-bit of information during a period of time. There are two main flavours: System DFF and standard DFF, with or without reset input

System DFF

The system D Flip-flop (Sys-DFF) captures the input data on every clock cycle. Therefore, this is is a component that is all the time reading information, at the system clock frecuency (very fast)

The input data at a given cycle n is captured on the rising edge of the system clock and output at the cycle n+1. Its initial value, (the value at cycle 0) can be set as a parameter. Its default value is 0

This is the Truth table

input (cycle n) output (cycle n+1)
0 0
1 1

Because the System DFF captures data at cycle n and output it at cycle n+1, it its said that it "Delays" the data 1 cycle. That is the reason why it is call D Flip-Flip. The D means "Delay"

NOTE: Notice that the DFF component has an nc output. It means Not connected. This output is NOT USED. It is placed there for aligning the input and output. These two pins, input (d) and output (q) are now on the same horizontal line. It allows us to connect many DFF in cascade keeping all of them in the same horizontal file (perfectly aligned)

Implementation

As the System D Flip-flop is a fundamental component, it is implemented directly in Verilog

This is the verilog code:

//-- Initial value
reg qi = INI;

//-- Capture the input data  
//-- on the rising edge of  
//-- the system clock
always @(posedge clk)
  qi <= d;
  
//-- Connect the register with the
//-- output
assign q = qi;

Example 1: Generating an initial 1-cycle pulse

In this example an initial pulse is generated using a system DFF. The pulse width is 1 cycle.

These are the values of the signal over time:

Cycle 0 cycle 1 Cycle 2 Cycle 3
1 0 0 0

The cycle 0 is the first cycle produced in the FPGA (After the FPGA is configured, the cycle 0 starts). The DFF contains initially 1 (its initial value, set by the top Init parameter)

In the next cycles, a value 0 is captured on the DFF

The output signal from the DFF is measurred with the LEDOscope. It allow us to see the first 4 cycles of a signal. The value for every cycle is display on an LED. After loading this circuit on the Alhambra-II board the state of the LEDs will be:

LED0 (cycle 0) LED 1 (cycle 1) LED 2 (cycle 2) LED 3 (cycle 3)
ON (1) OFF (0) OFF (0) OFF (0)

Example 2: Delaying a signal 2 cycles

In this example, the previous initial pulse is delayed two cycles. Any signal can be delay 1 cycle using a DFF. If we want to delay it two cycles, we should connect two DFF in cascade

In this table the values for the different signals in the circuit are shown:

Signal cycle 0 cycle 1 cycle 2 cycle 3
Initial pulse 1 0 0 0
DFF1 output 0 1 0 0
DFF2 output 0 0 1 0

The output of the DFF2, the one we are meassuring, is the same than the initial pulse, but delayed 2 cycles: It is 0 during cycles 0 and 1 and the pulse appears in cycle 2

When tested on the Alhambra-II board, we will see that pattern on the LEDs:

LED0 (cycle 0) LED 1 (cycle 1) LED 2 (cycle 2) LED 3 (cycle 3)
OFF (0) OFF (0) ON (1) OFF (0)

System DFF with reset

The System D Flip-flop with reset (Sys-DFF-rst) works exactly the same as the Sys-DFF: it captures the input data on every clock cycle. But it includes the rst input (with priority over d) for setting the DFF to its initial value (The one set in their Init top parameter)

This is the table that defines how this Flip-Flop works. The rst input has priority over the data input. When rst is 1, the output is always the initial value

rst d (cycle n) output (cycle n+1)
0 0 0
0 1 1
1 x Initial value

Implementation

The system DFF with input reset is implemented with a system DFF and a 1-bit 2-1 Multiplexer. While the reset input (rst) is not active (0), the Sys-DFF is capturing the input data (d). When the reset input is active, the initial value is captured.

Notice that the priority is on the rst pin, as it is used for selecting the multiplexer. No matter what value is in d if the rst input is 1

The Sys-DFF-rst-verilog is exactly the same than the Sys-DFF-rst but implemented directly in verilog:

This is the verilog code:

//-- Initial value
reg qi = INI;

always @(posedge clk)
begin
 
 //-- The priority is for
 //-- the reset input
 if (rst == 1'b1)
   qi <= INI;
   
 //-- If reset is not active,
 //-- then capture the input data
 else
   qi <= d;
 
end

//-- Connect the register with the
//-- output
assign q = qi;

Example 3: Generating a two cycles pulse

A two cycles pulse is generated using a Sys-DFF with reset

The generated signal is captured with the LEDOscope and shown on the four LEDs:

LED0 (cycle 0) LED1 (cycle 1) LED (cycle 2) LED (cycle 3)
0 1 1 0

Let's check how this output is generated. Let's assume first that we are using a sys-DFF without reset. The output signal will be s step function: it starts with 0 and it captures 1's in the next cycles:

Signal Cycle 0 Cycle 1 Cycle 2 Cycle 3
Sys-DFF 0 1 1 1

Now let's delay this signal by 1 cycle, using another sys-DFF:

Signal Cycle 0 Cycle 1 Cycle 2 Cycle 3
Sys-DFF delayed 0 0 1 1

Let's connect this delayed signal back to the reset input of the initial sys-DFF. At cycle 2 the reset is 1, therefore the sys-DFF is changed to its initial value in the next cycle, getting the final output signal

Signal Cycle 0 Cycle 1 Cycle 2 Cycle 3
Sys-DFF-rst 0 1 1 0
rst 0 0 1 1

System DFF with load

The System D Flip-flop with load (Sys-DFF-load) works exactly the same as the Sys-DFF: it captures the input data on every clock cycle. But its inputs come from the input si (serial input). When the load input is active, the data is capture from the d input instead of si. This special kind of flip-flop is used for implemeting shift registers

This is the table that defines how this Flip-Flop works

load d (cycle n) si (cycle n) output (cycle n+1)
0 d si si
1 d si d

Implementation

The system DFF with load is implemented with a system DFF and a 1-bit 2-1 Multiplexer. While the load input (load) is not active (0), the Sys-DFF is capturing the serial data (si). When the load input is active, the d input is captured.

The Sys-DFF-ld-verilog is exactly the same than the Sys-DFF-ld but implemented directly in verilog:

This is the verilog code:

//-- Initial value
reg qi = INI;

always @(posedge clk)
begin
 
 //-- When load is active
 //-- the input data is captured
 if (load == 1'b1)
   qi <= d;
 else
   //-- if not, the serial input is captured
   qi <= si;
 
end

//-- Connect the register with the
//-- output
assign q = qi;

System DFF with load and reset

The System D Flip-flop with load and reset (Sys-DFF-ld-rst) works exactly the same as the Sys-DFF-ld, but includes the rst input. When rst is 1, the Flip-flop is loaded with its initial value. rst has more priority than load

This is the table that defines how this Flip-Flop works

rst load d (cycle n) si (cycle n) output (cycle n+1)
0 0 d si si
0 1 d si d
1 x x x Initial value

Implementation

The system DFF with load and reset is implemented with a system DFF and two 1-bit 2-1 Multiplexers in cascade

The Sys-DFF-ld-rst-verilog is exactly the same than the Sys-DFF-ld-rst but implemented directly in verilog:

This is the verilog code:

//-- Initial value
reg qi = INI;

always @(posedge clk)
begin
 
 //-- Reset the circuit
 if (rst == 1'b1)
   qi <= INI;
   
 else
 
   //-- When load is active
   //-- the input data is captured
   if (load == 1'b1)
     qi <= d;
   else
     //-- if not, the serial input is captured
     qi <= si;
 
end

//-- Connect the register with the
//-- output
assign q = qi;

DFF

The standard D flip-flop has two inputs: data (d) and load. It only captures the input when load is active (1). If load is 0, the input is ignored and the flip-flops does not change its value

Its behaviour is described on this table:

load d output (next cycle) Description
0 0 No change The DFF does not change its value
0 1 No change The DFF does not change its value
1 0 0 The value 0 is captured
1 1 1 The value 1 is captured

Notice that the DFF behaves as a Sys-DFF when load is 1.

The sys-DFF let's us to store information only for one cycle. In the next cycle a new value will be captured (the sys-DFF is capturing all the time). With the DFF we can retain the information all the time we want. It only changes when loadis 1

The pulse symbol on the load input means that the DFF will capture one data per 1-cycle pulse. If you apply a 2-cycles pulse, the DFF will perform two consecutives captures (on two consecutive cycles)

A DFF with the load input connected to the 1 constant it is equivalent to a System Flip-Flop (Sys-DFF): It will capture the input on every system clock cycle

Implementation

The DFF is implemented with a system DFF and a 1-bit 2-1 Multiplexer. While the load input (rst) is not active (0), the Sys-DFF is capturing its own value (curr_bit), so there is no change. When load is 1, the input data is captured.

The DFF-verilog is exactly the same than the DFF but implemented directly in verilog:

This is the verilog code:

//-- Initial value
reg qi = INI;

always @(posedge clk)
begin
 
 //-- When load is active
 //-- the input data is captured
 if (load == 1'b1)
   qi <= d;
 
end

//-- Connect the register with the
//-- output
assign q = qi;

Example 4: Turning on an LED with the button

This is the classic example of turning ON an LED. When the SW1 button is pressed, the D Flip-flop captures a 1, and the LED is turned on

DFF with reset

The D Flip-flop with reset (DFF-rst) works exactly the same as the DFF, but it includes the rst input (with priority over load) for setting the DFF to its initial value

This is the table that defines how this Flip-Flop works. The rst input has priority over the load input. When rst is 1, the output is always the initial value

rst load d (cycle n) output (cycle n+1)
0 0 0 no change
0 0 1 no change
0 1 0 0
0 1 1 1
1 x x Initial value

Implementation

The DFF-rst is implemented with a system DFF-rst and a 1-bit 2-1 Multiplexer. While the load input is not active (0), the Sys-DFF-rst is capturing its own value (curr_bit), so there is no change. When load is 1, the input data is captured. When the rst input is set to 1, the Flip-flop changes to its initial value. The rst has priority over load

The DFF-rst-verilog is exactly the same than the DFF-rst but implemented directly in verilog:

This is the verilog code:

//-- Initial value
reg qi = INI;

always @(posedge clk)
begin
 
 //-- Priority for rst
 if (rst == 1'b1)
   qi <=INI;
   
 //-- Load input data
 else if (load == 1'b1)
   qi <= d;
 
end

//-- Connect the register with the
//-- output
assign q = qi;

Example 5: Turning an LED on and off with two buttons

The D Flip-Flop with reset is used for turning on and off an LED. When the button sw1 is pressed, a 1 is captured on the Flip-flop and the LED is turned on. If the sw2 button is pressed, the Flip-Flop is reset to 0

T Flip-Flops

The T Flip-Flops start with an initial value and toggles it according to an event. There are two main flavours: System TFF and standard TFF, with or without reset input

System TFF

The system T Flip-flop (Sys-TFF) toggles on every clock cycle. Therefore, this is is a component that is all the time toggling, at the system clock frecuency (very fast). The event that causes it to toggle is a rising edge on the system clock

If its initial value is 0, this is the output: 0, 1, 0, 1, 0, 1, 0, ...

This is the Truth table

Value at cycle n Value at cycle n+1
0 1
1 0

The T from TFF comes from "Toggle"

Implementation

The System T Flip-Flop is implemented from a Sys-DFF and a NOT gate. The value at cycle n is inverted and read in the next cycle (n+1). Therefore toggling the Flip-Flop on every clock cycle

The Sys-TFF-Verilog block is exactly the same as Sys-TFF but implemented in verilog:

This is the verilog code:

//-- Initial value
reg qi = INI;

//-- TFF
always @(posedge clk)

  //-- Toggle the Output
  //-- on every clock cycle
  qi <= ~qi;
  
//-- Connect the register with the
//-- output
assign q = qi;

Example 6: Watching the TFF with the LEDOscope

The output of the Sys-TFF is connected to a 4-bits LEDOscope so that we can watch its values from the Cycles 0 to 3

In this table the values of the sys-TFF output signal are shown:

Cycle 0 (LED0) Cycle 1 (LED1) Cycle 2 (LED2) Cycle 3 (LED3)
0 1 0 1

In addition, the output is connected directly to the LED7. As it is an oscilating signal (ON-OFF-ON-...), the LED7 is turned ON but with less brightness. To appreciate its brightness the LED6 is also turned ON with a constant 1 (So that it has the maximum possible bright)

System TFF with reset

The System T Flip-flop with reset (Sys-TFF-rst) works exactly the same as the Sys-TFF: it toggles on every clock cycle. But it includes the rst input for setting the TFF to its initial value (defined by its Init top parameter)

This is the table that defines how this Flip-Flop works. When rst is 1, the output is always the initial value

rst Current value (cycle n) output (cycle n+1)
0 0 1
0 1 0
1 x Initial value

Implementation

The system TFF with input reset is implemented with a system TFF and a NOT gate. While the reset input (rst) is not active (0), the Sys-TFF-rst is toggling. When the reset input is active, the initial value is captured.

The Sys-DFF-rst-verilog is exactly the same than the Sys-DFF-rst but implemented directly in verilog:

This is the verilog code:

//-- Initial value
reg qi = INI;

//-- TFF
always @(posedge clk)

  //-- Reset with priority
  if (rst == 1'b1)
    qi <= INI;
    
  else
    //-- Toggle the Output
    //-- on every clock cycle
    qi <= ~qi;
  
//-- Connect the register with the
//-- output
assign q = qi;

Example 7: Watching the TFF-rst with the LEDOscope

The output of the Sys-TFF-rst is connected to a 4-bits LEDOscope so that we can watch its values from the Cycles 0 to 3

In this table the values of the sys-TFF-rst output signal are shown:

Cycle 0 (LED0) Cycle 1 (LED1) Cycle 2 (LED2) Cycle 3 (LED3)
0 1 0 0

Its output is similar to that of the example 6 (sys-TFF), but now the value at cycle 3 is 0 because its reset input is set to 1 in cycle 2. The reset signal comes from the D Flip-flop that is 0 at cycles 0 and 1. At cycle 2 it captures a 1, so that it reset the sys-TFF-rst and ouput 0 at cycle 3

TFF

The standard T flip-flop has one input: toggle (t). It only toggles when the toggle input is active (1). If toggle is 0 it remains with the same value. The event that causes it to toggle is a 1 in the input toggle signal

Its behaviour is described on this table:

toggle current value output (next cycle) Description
0 0 0 No change
0 1 0 No change
1 0 1 Toggles
1 1 0 Toggles

Notice that the TFF behaves as a Sys-TFF when toggle is 1.

Implementation

The TFF is implemented with a DFF and a Not gate. The data input receives its inverted output. When the toogle input is active, the DFF captures its inverse value. If toogle is 0, it remains with the same value.

The TFF-verilog is exactly the same than the TFF but implemented directly in verilog:

This is the verilog code:

//-- Initial value
reg qi = INI;

always @(posedge clk)
begin
 
 //-- check the toogle input
 if (t == 1'b1)
   qi <= ~ qi;
 
end

//-- Connect the register with the
//-- output
assign q = qi;

Example 8: Toggling a LED with a button

The TFF is connected to an LED. When the button is pressed, the LED is toggled

TFF with reset

The T Flip-flop with reset (TFF-rst) works exactly the same as the TFF, but it includes the rst input (with priority over toggle) for setting the TFF to its initial value

This is the table that defines how this Flip-Flop works. The rst input has priority over the toggle input. When rst is 1, the output is always the initial value

rst toggle Current value (cycle n) output (cycle n+1) Description
0 0 0 0 No change
0 0 1 1 No change
0 1 0 1 Toggle
0 1 1 0 Toggle
1 x x Initial value

Implementation

The TFF with reset is implemented with a DFF with reset and a Not gate. While the reset input (rst) is not active (0), the DFF-rst is capturing the input data (d) when load is 1. This data comes from its inverted output. When the reset input is active, the initial value is captured

The TFF-rst-verilog is exactly the same than the TFF-rst but implemented directly in verilog:

This is the verilog code:

//-- Initial value
reg qi = INI;

always @(posedge clk)
begin
 
 //-- The priority is for
 //-- the reset input
 if (rst == 1'b1)
   qi <= INI;
   
 //-- If reset is not active,
 //-- check the toogle input
 else if (t == 1'b1)
   qi <= ~ qi;
 
end

//-- Connect the register with the
//-- output
assign q = qi;

Example 9: TFF-rst: Manual testing

The LED is toggle with the SW1 button. When the button SW2 is pressed, the T Flip-Flop is reset

RS Flip-Flops

The RS Flip-Flops have two inputs called reset and set. When reset is 1, the Flip-Flop value changes to 0. When 'set' is 1, the value changes to 1.

This is the table that describes its behaviour:

reset input set input current value output (next cycle) Descripttion
0 0 0 0 No change
0 0 1 1 No change
0 1 x 1 Set value to 1
1 0 x 0 Set value to 0 (Reset)

What happens if both inputs, reset and set are active at the same time? In this case, the behaviour depends on the priority given to the inputs. There are two flavours: RS-FF with priority on set and RS-FF with priority on reset

RS-FF with priority on set

If set is active, the Flip-flop turns 1, no matter what the value on the reset input is.

This is the table:

reset input set input current value output (next cycle) Descripttion
0 0 0 0 No change
0 0 1 1 No change
1 0 x 0 Set value to 0 (Reset)
x 1 x 1 Set value to 1 (Priority on set)

Implementation

The RS Flip-flops are implemented from a System DFF with two 1-bit 2-1 Muxes in cascade.

The order of connection determines the priority. In the case of the RS with priority on set, the first mux is controlled by the set input. If set is 1, a constant 1 will be captured by the Sys-DFF in the next cycle, no matter what is the value for the reset signal

If set is 0, the data input comes from the second mux, which input is selected by the reset input. If reset is 1, a constant 0 is captured in the System DFF. If not, its current value is captured (so that there is no change on the flip-flop)

The RS-FF-set-verilog is exactly the same than RS-FF-set but implemented in Verilog

This is the verilog code:

//-- Initial value
reg qi = INI;

always @(posedge clk)
begin

  //-- Priority on set
  //-- It is first checked
  if (set == 1'b1) 
    qi <= 1'b1;
    
  //-- Second: check reset
  else if (reset == 1'b1)
    qi <= 1'b0;
    
  //-- In any other case the FF
  //-- remains in its current 
  //-- state (no change)
end

//-- Connect the register with the
//-- output
assign q = qi;

Example 10: RS-FF-set: Manual testing

This is an example of manually testing the RS Flip-Flip with priority on Set. Buttons SW1 and SW2 act on set and reset respectively

RS-FF with priority on reset

If reset is active, the Flip-flop turns 0, no matter what the value on the set input is.

This is the table:

reset input set input current value output (next cycle) Descripttion
0 0 0 0 No change
0 0 1 1 No change
0 1 x 1 Set value to 1 (set)
1 x x 0 Set value to 0 (Priority on Reset)

Implementation

The implementation is similar to that of the RS-FF with priority on set: a System DFF and two 1-bit 2-1 Mux. But as the priority is on the Reset input, the two Mux are interchanged

The RS-FF-reset-verilog is exactly the same than RS-FF-reset but implemented in Verilog

This is the verilog code:

//-- Initial value
reg qi = INI;

always @(posedge clk)
begin

  //-- Priority on reset
  //-- It is first checked
  if (reset == 1'b1) 
    qi <= 1'b0;
    
  //-- Second: check set
  else if (set == 1'b1)
    qi <= 1'b1;
    
  //-- In any other case the FF
  //-- remains in its current 
  //-- state (no change)
end

//-- Connect the register with the
//-- output
assign q = qi;

Example 11: RS-FF-reset: Manual testing

This is an example of manually testing the RS Flip-Flip with priority on Reset. Buttons SW1 and SW2 act on set and reset respectively

TestBenches

The circuits used for testing all que components of this collection can be found on this collection:

  • IceFF-TB: Testbenches for the Flip-flops. It is intended for developers, not for final users

Translations

The collection can be translated to any language. Any translation is very welcome!! 😀️ If you want to translate it to your native languaje please follow these instructions: Translating the collection into your language. This instructions are for the iceK collection, but the translation procedure is the same for any other collection

Organization of the collection

The Organization of this collections is exactly the same than all the other collections. It consist of the following folders:

  • blocks: This is were the icestudio blocks are located, with all the elements of the collection, organized by subfolders
  • examples: Circuit examples ready to use in Icestudio. Inside this examples there are some special elements:
    • 00-Index.ice: Collection index. Here you will see some of the more important blocks that the collection contains
  • icons: Here you will find the SVG files for the icons used in the collection blocks. You can edit them or create new icons from them
    • block+icon: Some of the blocks in SVG, for using them in your documentations. These are some examples:
  • locale: Folder with the English texts and their translation into other languages
  • wiki: Images used in this wiki

This is the Index file:

  • 00-Index.ice:

Contributing to the collection

Contributions are welcome! 😀️

You can contribute in different manners:

  • Adding new blocks
  • Translating the collection to your language
  • Migrating the examples to more boards

These are the steps to follow for contributing:

  1. Fork the iceFF repo into your github account
  2. Clone it to your computer
  3. Install the collection as an external collection, so that you can access it from icestudio (See: Other uses: External collection)
  4. Create your own block
  5. Save it and click on Tools/Collection/Reload for using it and testing it
  6. Commit and push to your repo
  7. Emit a pull request

Important!

  • The main language is English: Create all your blocks and examples in English (the English text should be inside de .ice files). Then translate it to your local language (if you like), following the instructions mentioned here: Translating the collection into your language

  • The iceFF collection is ONLY FOR FLIP-FLOPS. If you want to contribute with other type of blocks, do it in its corresponding collection (iceK, iceGates, iceRegs, iceCoders...)

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