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Bump sway-core to use fuel-asm version 0.6 (#2193)
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* Bumped to 0.6, removed CIMV, CTMV & SLDC opcodes
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Braqzen authored Jul 1, 2022
1 parent 2e89868 commit 2597a02
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Showing 8 changed files with 20 additions and 88 deletions.
22 changes: 16 additions & 6 deletions Cargo.lock

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2 changes: 1 addition & 1 deletion forc/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -24,7 +24,7 @@ clap_complete = "3.1"
forc-pkg = { version = "0.16.2", path = "../forc-pkg" }
forc-util = { version = "0.16.2", path = "../forc-util" }
fs_extra = "1.2"
fuel-asm = "0.5"
fuel-asm = "0.6"
fuel-crypto = "0.5"
fuel-gql-client = { version = "0.9", default-features = false }
fuel-tx = "0.13"
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2 changes: 1 addition & 1 deletion sway-core/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ clap = { version = "3.1", features = ["derive"], optional = true }
derivative = "2.2.0"
dirs = "3.0"
either = "1.6"
fuel-asm = "0.5"
fuel-asm = "0.6"
fuel-crypto = "0.5"
fuel-tx = "0.13"
fuel-types = "0.5"
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9 changes: 0 additions & 9 deletions sway-core/src/asm_lang/allocated_ops.rs
Original file line number Diff line number Diff line change
Expand Up @@ -85,8 +85,6 @@ pub(crate) enum AllocatedOpcode {
SUBI(AllocatedRegister, AllocatedRegister, VirtualImmediate12),
XOR(AllocatedRegister, AllocatedRegister, AllocatedRegister),
XORI(AllocatedRegister, AllocatedRegister, VirtualImmediate12),
CIMV(AllocatedRegister, AllocatedRegister, AllocatedRegister),
CTMV(AllocatedRegister, AllocatedRegister),
JI(VirtualImmediate24),
JNEI(AllocatedRegister, AllocatedRegister, VirtualImmediate12),
JNZI(AllocatedRegister, VirtualImmediate18),
Expand Down Expand Up @@ -144,7 +142,6 @@ pub(crate) enum AllocatedOpcode {
),
MINT(AllocatedRegister),
RVRT(AllocatedRegister),
SLDC(AllocatedRegister, AllocatedRegister, AllocatedRegister),
SRW(AllocatedRegister, AllocatedRegister),
SRWQ(AllocatedRegister, AllocatedRegister),
SWW(AllocatedRegister, AllocatedRegister),
Expand Down Expand Up @@ -216,8 +213,6 @@ impl fmt::Display for AllocatedOp {
SUBI(a, b, c) => format!("subi {} {} {}", a, b, c),
XOR(a, b, c) => format!("xor {} {} {}", a, b, c),
XORI(a, b, c) => format!("xori {} {} {}", a, b, c),
CIMV(a, b, c) => format!("cimv {} {} {}", a, b, c),
CTMV(a, b) => format!("ctmv {} {}", a, b),
JI(a) => format!("ji {}", a),
JNEI(a, b, c) => format!("jnei {} {} {}", a, b, c),
JNZI(a, b) => format!("jnzi {} {}", a, b),
Expand Down Expand Up @@ -250,7 +245,6 @@ impl fmt::Display for AllocatedOp {
LOGD(a, b, c, d)=> format!("logd {} {} {} {}", a, b, c, d),
MINT(a) => format!("mint {}", a),
RVRT(a) => format!("rvrt {}", a),
SLDC(a, b, c) => format!("sldc {} {} {}", a, b, c),
SRW(a, b) => format!("srw {} {}", a, b),
SRWQ(a, b) => format!("srwq {} {}", a, b),
SWW(a, b) => format!("sww {} {}", a, b),
Expand Down Expand Up @@ -328,8 +322,6 @@ impl AllocatedOp {
SUBI(a, b, c) => VmOp::SUBI(a.to_register_id(), b.to_register_id(), c.value),
XOR (a, b, c) => VmOp::XOR (a.to_register_id(), b.to_register_id(), c.to_register_id()),
XORI(a, b, c) => VmOp::XORI(a.to_register_id(), b.to_register_id(), c.value),
CIMV(a, b, c) => VmOp::CIMV(a.to_register_id(), b.to_register_id(), c.to_register_id()),
CTMV(a, b) => VmOp::CTMV(a.to_register_id(), b.to_register_id()),
JI (a) => VmOp::JI (a.value),
JNEI(a, b, c) => VmOp::JNEI(a.to_register_id(), b.to_register_id(), c.value),
JNZI(a, b) => VmOp::JNZI(a.to_register_id(), b.value),
Expand Down Expand Up @@ -362,7 +354,6 @@ impl AllocatedOp {
LOGD(a, b, c, d)=> VmOp::LOGD(a.to_register_id(), b.to_register_id(), c.to_register_id(), d.to_register_id()),
MINT(a) => VmOp::MINT(a.to_register_id()),
RVRT(a) => VmOp::RVRT(a.to_register_id()),
SLDC(a, b, c) => VmOp::SLDC(a.to_register_id(), b.to_register_id(), c.to_register_id()),
SRW (a, b) => VmOp::SRW (a.to_register_id(), b.to_register_id()),
SRWQ(a, b) => VmOp::SRWQ(a.to_register_id(), b.to_register_id()),
SWW (a, b) => VmOp::SWW (a.to_register_id(), b.to_register_id()),
Expand Down
30 changes: 0 additions & 30 deletions sway-core/src/asm_lang/mod.rs
Original file line number Diff line number Diff line change
Expand Up @@ -544,24 +544,6 @@ impl Op {
);
VirtualOp::XORI(r1, r2, imm)
}
"cimv" => {
let (r1, r2, r3) = check!(
three_regs(args, immediate, whole_op_span),
return err(warnings, errors),
warnings,
errors
);
VirtualOp::CIMV(r1, r2, r3)
}
"ctmv" => {
let (r1, r2) = check!(
two_regs(args, immediate, whole_op_span),
return err(warnings, errors),
warnings,
errors
);
VirtualOp::CTMV(r1, r2)
}
"ji" => {
let imm = check!(
single_imm_24(args, immediate, whole_op_span),
Expand Down Expand Up @@ -841,15 +823,6 @@ impl Op {
);
VirtualOp::RVRT(r1)
}
"sldc" => {
let (r1, r2, r3) = check!(
three_regs(args, immediate, whole_op_span),
return err(warnings, errors),
warnings,
errors
);
VirtualOp::SLDC(r1, r2, r3)
}
"srw" => {
let (r1, r2) = check!(
two_regs(args, immediate, whole_op_span),
Expand Down Expand Up @@ -1376,8 +1349,6 @@ impl fmt::Display for Op {
SUBI(a, b, c) => format!("subi {} {} {}", a, b, c),
XOR(a, b, c) => format!("xor {} {} {}", a, b, c),
XORI(a, b, c) => format!("xori {} {} {}", a, b, c),
CIMV(a, b, c) => format!("cimv {} {} {}", a, b, c),
CTMV(a, b) => format!("ctmv {} {}", a, b),
JI(a) => format!("ji {}", a),
JNEI(a, b, c) => format!("jnei {} {} {}", a, b, c),
JNZI(a, b) => format!("jnzi {} {}", a, b),
Expand Down Expand Up @@ -1410,7 +1381,6 @@ impl fmt::Display for Op {
LOGD(a, b, c, d) => format!("logd {} {} {} {}", a, b, c, d),
MINT(a) => format!("mint {}", a),
RVRT(a) => format!("rvrt {}", a),
SLDC(a, b, c) => format!("sldc {} {} {}", a, b, c),
SRW(a, b) => format!("srw {} {}", a, b),
SRWQ(a, b) => format!("srwq {} {}", a, b),
SWW(a, b) => format!("sww {} {}", a, b),
Expand Down
39 changes: 0 additions & 39 deletions sway-core/src/asm_lang/virtual_ops.rs
Original file line number Diff line number Diff line change
Expand Up @@ -53,8 +53,6 @@ pub(crate) enum VirtualOp {
SUBI(VirtualRegister, VirtualRegister, VirtualImmediate12),
XOR(VirtualRegister, VirtualRegister, VirtualRegister),
XORI(VirtualRegister, VirtualRegister, VirtualImmediate12),
CIMV(VirtualRegister, VirtualRegister, VirtualRegister),
CTMV(VirtualRegister, VirtualRegister),
JI(VirtualImmediate24),
JNEI(VirtualRegister, VirtualRegister, VirtualImmediate12),
JNZI(VirtualRegister, VirtualImmediate18),
Expand Down Expand Up @@ -118,7 +116,6 @@ pub(crate) enum VirtualOp {
),
MINT(VirtualRegister),
RVRT(VirtualRegister),
SLDC(VirtualRegister, VirtualRegister, VirtualRegister),
SRW(VirtualRegister, VirtualRegister),
SRWQ(VirtualRegister, VirtualRegister),
SWW(VirtualRegister, VirtualRegister),
Expand Down Expand Up @@ -181,8 +178,6 @@ impl VirtualOp {
SUBI(r1, r2, _i) => vec![r1, r2],
XOR(r1, r2, r3) => vec![r1, r2, r3],
XORI(r1, r2, _i) => vec![r1, r2],
CIMV(r1, r2, r3) => vec![r1, r2, r3],
CTMV(r1, r2) => vec![r1, r2],
JI(_im) => vec![],
JNEI(r1, r2, _i) => vec![r1, r2],
JNZI(r1, _i) => vec![r1],
Expand Down Expand Up @@ -215,7 +210,6 @@ impl VirtualOp {
LOGD(r1, r2, r3, r4) => vec![r1, r2, r3, r4],
MINT(r1) => vec![r1],
RVRT(r1) => vec![r1],
SLDC(r1, r2, r3) => vec![r1, r2, r3],
SRW(r1, r2) => vec![r1, r2],
SRWQ(r1, r2) => vec![r1, r2],
SWW(r1, r2) => vec![r1, r2],
Expand Down Expand Up @@ -278,8 +272,6 @@ impl VirtualOp {
SUBI(_r1, r2, _i) => vec![r2],
XOR(_r1, r2, r3) => vec![r2, r3],
XORI(_r1, r2, _i) => vec![r2],
CIMV(_r1, r2, r3) => vec![r2, r3],
CTMV(_r1, r2) => vec![r2],
JI(_im) => vec![],
JNEI(r1, r2, _i) => vec![r1, r2],
JNZI(r1, _i) => vec![r1],
Expand Down Expand Up @@ -312,7 +304,6 @@ impl VirtualOp {
LOGD(r1, r2, r3, r4) => vec![r1, r2, r3, r4],
MINT(r1) => vec![r1],
RVRT(r1) => vec![r1],
SLDC(r1, r2, r3) => vec![r1, r2, r3],
SRW(_r1, r2) => vec![r2],
SRWQ(r1, r2) => vec![r1, r2],
SWW(r1, r2) => vec![r1, r2],
Expand Down Expand Up @@ -375,8 +366,6 @@ impl VirtualOp {
SUBI(r1, _r2, _i) => vec![r1],
XOR(r1, _r2, _r3) => vec![r1],
XORI(r1, _r2, _i) => vec![r1],
CIMV(r1, _r2, _r3) => vec![r1],
CTMV(r1, _r2) => vec![r1],
JI(_im) => vec![],
JNEI(_r1, _r2, _i) => vec![],
JNZI(_r1, _i) => vec![],
Expand Down Expand Up @@ -409,7 +398,6 @@ impl VirtualOp {
LOGD(_r1, _r2, _r3, _r4) => vec![],
MINT(_r1) => vec![],
RVRT(_r1) => vec![],
SLDC(_r1, _r2, _r3) => vec![],
SRW(r1, _r2) => vec![r1],
SRWQ(_r1, _r2) => vec![],
SWW(_r1, _r2) => vec![],
Expand Down Expand Up @@ -644,15 +632,6 @@ impl VirtualOp {
update_reg(reg_to_reg_map, r2),
i.clone(),
),
CIMV(r1, r2, r3) => Self::CIMV(
update_reg(reg_to_reg_map, r1),
update_reg(reg_to_reg_map, r2),
update_reg(reg_to_reg_map, r3),
),
CTMV(r1, r2) => Self::CTMV(
update_reg(reg_to_reg_map, r1),
update_reg(reg_to_reg_map, r2),
),
JI(_) => self.clone(),
JNEI(r1, r2, i) => Self::JNEI(
update_reg(reg_to_reg_map, r1),
Expand Down Expand Up @@ -761,11 +740,6 @@ impl VirtualOp {
),
MINT(r1) => Self::MINT(update_reg(reg_to_reg_map, r1)),
RVRT(reg1) => Self::RVRT(update_reg(reg_to_reg_map, reg1)),
SLDC(r1, r2, r3) => Self::SLDC(
update_reg(reg_to_reg_map, r1),
update_reg(reg_to_reg_map, r2),
update_reg(reg_to_reg_map, r3),
),
SRW(r1, r2) => Self::SRW(
update_reg(reg_to_reg_map, r1),
update_reg(reg_to_reg_map, r2),
Expand Down Expand Up @@ -1052,14 +1026,6 @@ impl VirtualOp {
map_reg(&mapping, reg2),
imm.clone(),
),
CIMV(reg1, reg2, reg3) => AllocatedOpcode::CIMV(
map_reg(&mapping, reg1),
map_reg(&mapping, reg2),
map_reg(&mapping, reg3),
),
CTMV(reg1, reg2) => {
AllocatedOpcode::CTMV(map_reg(&mapping, reg1), map_reg(&mapping, reg2))
}
JI(imm) => AllocatedOpcode::JI(imm.clone()),
JNEI(reg1, reg2, imm) => AllocatedOpcode::JNEI(
map_reg(&mapping, reg1),
Expand Down Expand Up @@ -1165,11 +1131,6 @@ impl VirtualOp {
),
MINT(reg1) => AllocatedOpcode::MINT(map_reg(&mapping, reg1)),
RVRT(reg1) => AllocatedOpcode::RVRT(map_reg(&mapping, reg1)),
SLDC(reg1, reg2, reg3) => AllocatedOpcode::SLDC(
map_reg(&mapping, reg1),
map_reg(&mapping, reg2),
map_reg(&mapping, reg3),
),
SRW(reg1, reg2) => {
AllocatedOpcode::SRW(map_reg(&mapping, reg1), map_reg(&mapping, reg2))
}
Expand Down
2 changes: 1 addition & 1 deletion sway-types/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@ repository = "https://github.com/FuelLabs/sway"
description = "Sway core types."

[dependencies]
fuel-asm = "0.5"
fuel-asm = "0.6"
fuel-crypto = "0.5"
fuel-tx = "0.13"
lazy_static = "1.4"
Expand Down
2 changes: 1 addition & 1 deletion test/Cargo.toml
Original file line number Diff line number Diff line change
Expand Up @@ -11,7 +11,7 @@ filecheck = "0.5"
forc = { path = "../forc", features = ["test"], default-features = false }
forc-pkg = { path = "../forc-pkg" }
forc-util = { path = "../forc-util" }
fuel-asm = "0.5"
fuel-asm = "0.6"
fuel-tx = "0.13"
fuel-vm = { version = "0.12", features = ["random"] }
gag = "1.0"
Expand Down

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