High-Performance Hardware Implementation of CRYSTALS-Dilithium

Hardware Design Group: CERG GMU

Primary Hardware Designers:

Luke Beckwith, lbeckwit@gmu.edu
Duc Nguyen, dnguye69@gmu.edu

Academic advisors/Program managers:

Kris Gaj, https://ece.gmu.edu/~kgaj/, kgaj@gmu.edu

Related Paper

A paper corresponding to this implementation was presented at the International Conference on Field-Programmable Technology (FPT'21) and is publicly available at ePrint and IEEE FPT.

Details

KAT, rtl_src, rtl_tb

This repository contains a high performance FPGA implementation of the Dilithium PQC signature algorithm written in Verilog. It contains a top module, "combined_top" which supports the operations of key generation, sign, and verify for security levels 2, 3, and 5. The three associated test benches show how to operate the module for each of these operation modes.

The design was verified in simulation using the standard 100 KATs generated by the reference implementation.

dilithium-256

This folder contains the high level code that emulates the NTT design. The implementation of NTT-2x2 are in both software, and hardware style. This code has improved upon previous works [17,18] as cited in the paper.

Citation

@INPROCEEDINGS{High_performance_Dilithium_21,
  author={Beckwith, Luke and Nguyen, Duc Tri and Gaj, Kris},
  booktitle={2021 International Conference on Field-Programmable Technology (ICFPT)}, 
  title={High-Performance Hardware Implementation of CRYSTALS-Dilithium}, 
  year={2021},
  pages={1-10},
  doi={10.1109/ICFPT52863.2021.9609917}}