Avoid breaking up bitvectors in Verilog output

[atomb]

Previously, when translating What4 to Verilog, all VVector values were translated into multiple Verilog ports, one for each element. Only VWord values were translated into Verilog bitvectors. Now, VVector values with Boolean elements also get translated into Verilog bitvectors.

[robdockins]

I think you can probably just return [] here? I think it's better to avoid failure cases if we can.

[atomb]

I guess the consideration is whether this function should be generic (which it otherwise mostly is) or should be specific to Verilog generation. Verilog doesn't allow vectors of size zero, so in the latter case this is the result we want. At the same time, I also like to avoid failure cases whenever possible... And I'd prefer to do something other than fail.

[robdockins]

Looking at this some more, I think this will fail on empty vectors at any type, which you probably also don't want.

[atomb]

Oh, and now that I look further I think your previous suggestion was right. Returning an empty list for a zero-size bit vector will result in no value on the Verilog side, not an empty value, so it'll be fine. I'll update it so that any zero-size vector will go through okay.

[robdockins]

Looks good to me.