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RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

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Gchauvon/core-v-xif

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CORE-V X-Interface

The CORE-V X-Interface (core-v-xif) is a RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions for existing RISC-V processors.

It features independent channels for accelerator-agnostic offloading of instructions and writeback of the result(s).

Documentation

The CORE-V XIF user manual can be found in the docs folder and it is captured in reStructuredText, rendered to html using Sphinx. These documents are viewable using readthedocs and can be viewed here.

Changelog

A changelog is generated automatically in the documentation from the individual pull requests. Pull requests labeled with ignore-for-release are ignored for the changelog generation.

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RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions

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