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access.direct.multiplexer: add stream interfaces to FIFO ports.
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whitequark committed Apr 20, 2024
1 parent b2f7d34 commit 48d57a3
Showing 1 changed file with 12 additions and 0 deletions.
12 changes: 12 additions & 0 deletions software/glasgow/access/direct/multiplexer.py
Original file line number Diff line number Diff line change
@@ -1,6 +1,8 @@
import logging
from amaranth import *
from amaranth.lib import wiring

from ...gateware import stream
from .. import AccessMultiplexer, AccessMultiplexerInterface


Expand Down Expand Up @@ -31,6 +33,11 @@ def __init__(self, fifo):
self.r_rdy = Signal()
self.r_data = fifo.r_data

self.r_stream = stream.Signature(8).create()
self.r_stream.payload = self.r_data
self.r_stream.valid = self.r_rdy
self.r_stream.ready = self.r_en

def elaborate(self, platform):
fifo = self._fifo

Expand Down Expand Up @@ -70,6 +77,11 @@ def __init__(self, fifo):
self.w_data = fifo.w_data
self.flush = fifo.flush

self.w_stream = stream.Signature(8).flip().create()
self.w_stream.payload = self.w_data
self.w_stream.valid = self.w_en
self.w_stream.ready = self.w_rdy

def elaborate(self, platform):
fifo = self._fifo

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