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1. cv32e41s cv32e41s Public

   Forked from openhwgroup/cv32e40s

   4 stage, in-order, secure RISC-V core based on the CV32E40S

   SystemVerilog 3

2. RISC-V-Memory-Protection-Table RISC-V-Memory-Protection-Table Public

   This repo provides an open-source system verilog implementation for the Memory Protection Table (MPT), compliant with the official RISC-V specification. It supports both 64 and 32 bits systems.

   SystemVerilog 3

3. CV64A6T CV64A6T Public

   Forked from openhwgroup/cva6

   The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

   Assembly 2

4. cva5 cva5 Public

   Forked from openhwgroup/cva5

   CVA5 - Interfaceless

   SystemVerilog 1

5. bourbon-ristretto-32-riscv bourbon-ristretto-32-riscv Public

   A 32-bit RISC-V core built just for fun and learning purposes

   SystemVerilog

6. JNES-a-Java-NES-Emulator JNES-a-Java-NES-Emulator Public

   A Java NES emulator developed during Mc.S. in collaboration with Francesco Vitale and Daniele Ottaviano

   Java