RISC V Simulator

This is a project of CS204 (Computer Architecture) of RISC V Simulator.

The project is divided into three phases:

Phase 1:

• Implemented single cycle design with various instructions of RISC V

Phase 2:

• Implemented five-stage pipeline with stages IF, DE, EX, MA, WB.
• Implemented data forwarding and data stalling to remove hazards
• Implemented branch prediction to reduce stalls

Phase 3:

• Implemented cache memory
• Implemented various cache replacement policies such as FIFO, LRU, LFU and Random