GitHub - Hec7or-Uni/aoc2-tf-1

Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
ALU.vhd		ALU.vhd
BReg.vhd		BReg.vhd
Banco_EX.vhd		Banco_EX.vhd
Banco_EX_FP.vhd		Banco_EX_FP.vhd
Banco_ID.vhd		Banco_ID.vhd
Banco_MEM.vhd		Banco_MEM.vhd
Banco_MEM_FP.vhd		Banco_MEM_FP.vhd
Banco_WB.vhd		Banco_WB.vhd
Banco_WB_FP.vhd		Banco_WB_FP.vhd
Codigo_test_2022_P1.pdf		Codigo_test_2022_P1.pdf
Ext_signo.vhd		Ext_signo.vhd
Memoria.pdf		Memoria.pdf
Mips_segmentado.vhd		Mips_segmentado.vhd
UA.vhd		UA.vhd
UC_Mips.vhd		UC_Mips.vhd
UD.vhd		UD.vhd
add_Fp_trst.vhd		add_Fp_trst.vhd
adder32.vhd		adder32.vhd
bits_shifter.vhd		bits_shifter.vhd
counter.vhd		counter.vhd
fpadd.vhd		fpadd.vhd
hot_asm.conf		hot_asm.conf
memoriaRAM_D.vhd		memoriaRAM_D.vhd
memoriaRAM_D_fibonacci.vhd		memoriaRAM_D_fibonacci.vhd
memoriaRAM_I.vhd		memoriaRAM_I.vhd
memoriaRAM_I_fibonacci.vhd		memoriaRAM_I_fibonacci.vhd
memoriaRAM_I_nops.vhd		memoriaRAM_I_nops.vhd
memoriaRAM_I_test_P1.vhd		memoriaRAM_I_test_P1.vhd
memoriaRAM_test_P1.vhd		memoriaRAM_test_P1.vhd
mux2_1.vhd		mux2_1.vhd
mux2_5bits.vhd		mux2_5bits.vhd
mux4_1_32bits.vhd		mux4_1_32bits.vhd
reg32.vhd		reg32.vhd
testbench_Mips.vhd		testbench_Mips.vhd
wave.do		wave.do