Merge pull request zephyrproject-rtos#5 from HoZHel/steval-idb012v1

boards: st: Add STEVAL-IDB012V1 board

boards/st/steval_idb011v2/Kconfig.board → boards/st/steval_idb011v2/Kconfig.steval_idb011v2

@@ -1,4 +1,4 @@
-# BLUENRG-232 board configuration
+# BLUENRG-355 board configuration
 
 # SPDX-License-Identifier: Apache-2.0
 

boards/st/steval_idb012v1/Kconfig.defconfig

@@ -0,0 +1,26 @@
+# STEVAL-IDB012V1 board configuration
+
+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+if BOARD_STEVAL_IDB012V1
+
+config BOARD
+	default "steval_idb012v1"
+
+if BT
+
+choice BT_HCI_BUS_TYPE
+	default BT_STM32WB0
+endchoice
+
+choice BT_RECV_CONTEXT
+	default BT_RECV_WORKQ_BT
+endchoice
+
+config BT_HCI_ACL_FLOW_CONTROL
+	default n
+
+endif # BT
+
+endif # BOARD_STEVAL_IDB012V1

boards/st/steval_idb012v1/Kconfig.steval_idb012v1

@@ -0,0 +1,6 @@
+# Copyright (c) 2024 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+config BOARD_STEVAL_IDB012V1
+	bool "BLUENRG-LPS Evaluation Board"
+	depends on SOC_BLUENRG_LPS

boards/st/steval_idb012v1/board.cmake

@@ -0,0 +1,3 @@
+# SPDX-License-Identifier: Apache-2.0
+
+include(${ZEPHYR_BASE}/boards/common/openocd.board.cmake)

boards/st/steval_idb012v1/board.yml

@@ -0,0 +1,5 @@
+board:
+  name: steval_idb012v1
+  vendor: st
+  socs:
+    - name: bluenrg_lps

boards/st/steval_idb012v1/steval_idb012v1.dts

@@ -0,0 +1,122 @@
+/*
+ * Copyright (c) 2024 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/dts-v1/;
+#include <st/bluenrg/bluenrg_lps.dtsi>
+#include <st/bluenrg_3/bluenrg-332.dtsi>
+
+/ {
+	model = "STMicroelectronics BLUENRG_LPS-STEVAL_IDB012V1 board";
+	compatible = "st,bluenrg_lp-steval_idb012v1";
+
+	chosen {
+		zephyr,sram = &sram0;
+		zephyr,flash = &flash0;
+		zephyr,console = &usart1;
+		zephyr,shell-uart = &usart1;
+	};
+	leds {
+		compatible = "gpio-leds";
+		green_led_2: led_3 {
+			gpios = <&gpiob 4 GPIO_ACTIVE_LOW>;
+			label = "User LD1";
+		};
+		red_led_2: led_4 {
+			gpios = <&gpiob 2 GPIO_ACTIVE_LOW>;
+			label = "User LD2";
+		};
+		rgb_led_1: led_5 {
+			gpios = <&gpiob 1 GPIO_ACTIVE_LOW>;
+			label = "User LD3";
+		};
+	};
+
+	gpio_keys {
+		compatible = "gpio-keys";
+		user_button1: button1 {
+			label = "User Button 1";
+			gpios = <&gpioa 10 GPIO_ACTIVE_HIGH>;
+		};
+		user_button2: button2 {
+			label = "User Button 2";
+			gpios = <&gpiob 5 GPIO_ACTIVE_HIGH>;
+		};
+	};
+	aliases {
+		led0 = &green_led_2;
+		led1 = &red_led_2;
+		led2 = &rgb_led_1;
+		sw0 = &user_button1;
+		sw1 = &user_button2;
+	};
+
+};
+
+&clk_hse {
+	hse-bypass;
+	clock-frequency = <DT_FREQ_M(8)>; /* to be reviewed, possibly ignored by code */
+	status = "okay";
+};
+
+&pll {
+	clocks = <&clk_hse>;
+	mul = <8>;
+	div = <2>;
+	status = "okay";
+};
+
+&rcc {
+	clocks = <&pll>;
+	clock-frequency = <DT_FREQ_M(32)>;
+	ahb-prescaler = <1>;
+	apb1-prescaler = <1>;
+	apb2-prescaler = <1>;
+};
+
+&usart1 {
+	pinctrl-0 = <&usart1_tx_pa1 &usart1_rx_pb0>;
+	pinctrl-names="default";
+	current-speed = <115200>;
+	status = "okay";
+};
+
+&gpiob {
+	status = "okay";
+};
+
+&gpioa {
+	status = "okay";
+};
+
+&flash0 {
+	partitions {
+		compatible = "fixed-partitions";
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		/* Set 4KB of storage at the end of 192KB flash */
+		storage_partition: partition@2f000 {
+			label = "storage";
+			reg = <0x0002f000 DT_SIZE_K(4)>;
+
+		};
+	};
+};
+
+&rng {
+	status = "okay";
+};
+
+/*
+ *
+ * &adc1 {
+ *	 status = "okay";
+ * };
+ *
+ * &spi1 {
+ *	 status = "okay";
+ * };
+ */

boards/st/steval_idb012v1/steval_idb012v1.yaml

@@ -0,0 +1,12 @@
+identifier: bluenrg_lps
+name: BLUENRG_LPS
+type: mcu
+arch: arm
+toolchain:
+  - zephyr
+  - gnuarmemb
+  - xtools
+supported:
+  - counter
+ram: 24
+flash: 192

boards/st/steval_idb012v1/steval_idb012v1_defconfig

@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: Apache-2.0
+
+# Zephyr Kernel Configuration
+CONFIG_SOC_SERIES_BLUENRG_3=y
+
+# Platform Configuration
+CONFIG_SOC_BLUENRG_LPS=y
+
+# TBD_st to be checked for relocation
+CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=64000000
+
+# # Enable MPU
+# CONFIG_ARM_MPU=y
+
+# Serial Drivers
+CONFIG_SERIAL=y
+CONFIG_UART_INTERRUPT_DRIVEN=n
+# enable console
+CONFIG_CONSOLE=y
+CONFIG_UART_CONSOLE=y
+
+# GPIO Controller
+CONFIG_GPIO=y
+
+# Enable Clocks
+CONFIG_CLOCK_CONTROL=y
+CONFIG_CLOCK_CONTROL_BLUENRG_3=y
+
+# enable pin controller
+CONFIG_PINCTRL=y

boards/st/steval_idb012v1/support/openocd.cfg

@@ -0,0 +1,7 @@
+source [find interface/cmsis-dap.cfg]
+
+transport select swd
+
+set CHIPNAME bluenrg_lps
+
+source [find target/bluenrg-x.cfg]

drivers/clock_control/clock_bluenrglp.c

@@ -458,12 +458,12 @@ uint8_t SystemClockConfig(uint8_t SysClk)
     return ret_val;
   }
 
-#ifdef CONFIG_SOC_BLUENRG_LP
+#if defined(CONFIG_SOC_BLUENRG_LP) || defined(CONFIG_SOC_BLUENRG_LPS)
   /* BlueNRG_LP cut 1.0 not support DIRECT HSE configuration */
   if ((SysClk == SYSCLK_DIRECT_HSE) && (((LL_SYSCFG_GetDeviceVersion()<<4)|LL_SYSCFG_GetDeviceRevision()) == LL_BLUENRG_LP_CUT_10)) {
     return SYSTEM_CONFIG_DIRECT_HSE_NOT_SUPPORTED;
   }
-#endif
+#endif /* defined(CONFIG_SOC_BLUENRG_LP) || defined(CONFIG_SOC_BLUENRG_LPS) */
 
   if (SysClk != SYSCLK_DIRECT_HSE) {
     /* System PLL Clock configuration */

drivers/gpio/CMakeLists.txt

@@ -92,7 +92,7 @@ zephyr_library_sources_ifdef(CONFIG_GPIO_RENESAS_RA gpio_renesas_ra.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_ENE_KB1200 gpio_ene_kb1200.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_RZT2M    gpio_rzt2m.c)
 zephyr_library_sources_ifdef(CONFIG_GPIO_AMBIQ      gpio_ambiq.c)
-zephyr_library_sources_ifdef(CONFIG_GPIO_BLUENRG_3  gpio_bluenrg.c)
+zephyr_library_sources_ifdef(CONFIG_GPIO_BLUENRG  gpio_bluenrg.c)
 
 if (CONFIG_GPIO_EMUL_SDL)
   zephyr_library_sources(gpio_emul_sdl.c)

drivers/gpio/Kconfig.bluenrg

@@ -3,7 +3,7 @@
 # Copyright (c) 2016 Open-RnD Sp. z o.o.
 # SPDX-License-Identifier: Apache-2.0
 
-config GPIO_BLUENRG_3
+config GPIO_BLUENRG
 	bool "GPIO Driver for BlueNRG-LPx Series of MCUs"
 	default y
 	depends on DT_HAS_ST_STM32_GPIO_ENABLED && SOC_SERIES_BLUENRG_3