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autodef支持自动识别信号的位宽吗 #46

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joy20182018 opened this issue Jan 24, 2024 · 1 comment

joy20182018 commented Jan 24, 2024

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BossKen1995 commented May 17, 2024 •

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亲测是支持的，但是某些情况识别不到例化模块的wire，比如例化模块的所在verilog文件中定义了多个module，例化的模块不是第一个module，好像就找不到

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