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Add strip assertions flag
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Part 1 (this pr): add `iree-opt-strip-assertions` to CI.

Part 2: remove flag usage and make this default.

Issue: iree-org#1900

Signed-off-by: Ian Wood <ianwood2024@u.northwestern.edu>
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IanWood1 committed Nov 5, 2024
1 parent a757965 commit da92beb
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Showing 2 changed files with 3 additions and 2 deletions.
4 changes: 2 additions & 2 deletions .github/workflows/pkgci_regression_test.yml
Original file line number Diff line number Diff line change
Expand Up @@ -221,7 +221,7 @@ jobs:
--goldentime-rocm-clip-ms 18.5 \
--goldentime-rocm-vae-ms 337.0 \
--goldendispatch-rocm-unet 1531 \
--goldendispatch-rocm-clip 1141 \
--goldendispatch-rocm-clip 1139 \
--goldendispatch-rocm-vae 246 \
--goldensize-rocm-unet-bytes 2280000 \
--goldensize-rocm-clip-bytes 860000 \
Expand All @@ -242,7 +242,7 @@ jobs:
--goldentime-rocm-clip-ms 15.5 \
--goldentime-rocm-vae-ms 80.0 \
--goldendispatch-rocm-unet 1531 \
--goldendispatch-rocm-clip 1141 \
--goldendispatch-rocm-clip 1139 \
--goldendispatch-rocm-vae 246 \
--goldensize-rocm-unet-bytes 2270000 \
--goldensize-rocm-clip-bytes 860000 \
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1 change: 1 addition & 0 deletions experimental/benchmarks/sdxl/benchmark_sdxl_rocm.py
Original file line number Diff line number Diff line change
Expand Up @@ -56,6 +56,7 @@ def run_sdxl_rocm_benchmark(rocm_chip):
f"{benchmark_dir}/sdxl_pipeline_bench_f16.mlir",
"--iree-hal-target-backends=rocm",
f"--iree-hip-target={rocm_chip}",
"--iree-opt-strip-assertions=true",
"--iree-global-opt-propagate-transposes=true",
"--iree-codegen-llvmgpu-use-vector-distribution",
"--iree-codegen-gpu-native-math-precision=true",
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