CAT1 Cortex M0+ prebuilt images
Prebuilt application images are executed on the Cortex M0+ core of the CAT1 dual-core MCU. The images are provided as C arrays ready to be compiled as part of the Cortex M4/M7 application. The Cortex M0+ application code is placed to internal flash by the Cortex M4/M7 linker script.
What's Included?
CAT1A
-
This image starts CM4 core at CY_CORTEX_M4_APPL_ADDR
and puts CM0+ core into a deep sleep mode. (Check your device's
linker file (psoc6) or partition file (Traveo) for the
location of CY_CORTEX_M4_APPL_ADDR.) -
This image starts crypto server on CM0+ core,
starts CM4 core at CY_CORTEX_M4_APPL_ADDR=0x1000A000
and puts CM0+ core into a deep sleep mode. -
This image starts BLE controller on CM0+ core,
starts CM4 core at CY_CORTEX_M4_APPL_ADDR=0x10020000
and puts CM0+ core into a deep sleep mode. -
This image starts CM4 core at address corresponding
to Secure Boot policy, sets required security settings,
initializes and executes code of Protected Register Access
driver, puts CM0+ core into a deep sleep mode.
CAT1C
-
This image is meant for dual CM7 core (CM7_0/1) CAT1C device applications. This image starts both CM7_0 and CM7_1 core at CY_CORTEX_M7_0_APPL_ADDR and CY_CORTEX_M7_1_APPL_ADDR respectively and puts CM0+ core into a deep sleep mode.
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This image is meant for single CM7 core (CM7_0) device applications. This image starts CM7_0 core at CY_CORTEX_M7_0_APPL_ADDR and puts CM0+ core into a deep sleep mode.
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COMPONENT_XMC7xDUAL_CM0P_SLEEP
This image is meant for dual CM7 core (CM7_0/1) XMC7xxx device. This image starts both CM7_0 and CM7_1 core at CY_CORTEX_M7_0_APPL_ADDR and CY_CORTEX_M7_1_APPL_ADDR respectively and puts CM0+ core into a deep sleep mode. Not recommended for new projects; use the COMPONENT_DUAL_CM0P_SLEEP for new projects.
-
This image is meant for single CM7 core (CM7_0) XMC7xxx device. This image starts CM7_0 core at CY_CORTEX_M7_0_APPL_ADDR and puts CM0+ core into a deep sleep mode. Not recommended for new projects; use the COMPONENT_CM0P_SLEEP for new projects.
What Changed?
v1.7.0
- BLESS FW update to v5.0.13.492
v1.6.0
- Adds CAT1C support for Traveo II Cluster 2D6M devices.
- Renames the CAT1C component names to be more generic. Previous XMC7x and XMC7xDUAL images are still available, but not recommended for new projects.
v1.5.0
- Adds new support for Traveo II Body Entry 512K and 2M devices, and updates CM0P allocations for TVIIBE1M device.
v1.4.0
- Built prebuilts with mtb-pdl-cat1 3.9.0
v1.3.0
- Production support added for Traveo II Body Entry devices.
v1.2.0
- BLESS FW update to v5.0.12.462
v1.1.0
- Driver maintenance and code efficiency enhancement.
- BLESS FW update to v5.0.11.449
v1.0.0
- Initial release
Known Issues in CAT1A M0+ prebuilt images:
i. With ble-example-hello-sensor app running in CY8CKIT-062-BLE, when Remote Device A is bonded, Remote Device B would have scanning/connecting issues.
Recovery is to delete the bonding of Remote Device A.
ii. While running BLE stress test cases, some times controller stops sending HostMsgFlushRecvCallBack to HOST for the sent messages. This blocks all further operations.
Recovery is to reset the board.
Product/Asset Specific Instructions
To pick which image is used in an application update the COMPONENTS variable in the Board Support Package (BSP)'s makefile. Depending on which image is selected, an update to the BSPs linker script may also be required to allocate the proper space for the CM0+ image and that the CM4 has the starting address listed above.
Supported Software and Tools
This version of the (CAT1 Cortex M0+ prebuilt images) was validated for compatibility with the following Software and Tools:
| Software and Tools | Version |
|---|---|
| GCC Compiler | 11.3.1 |
| IAR Compiler | 9.3 |
| ARM Compiler 6 | 6.16 |
More information
Use the following links for more information, as needed:
© Cypress Semiconductor Corporation (an Infineon company), 2024.