More fixes for sleep and clocking stuff on MIMXRT105x (ARMmbed#158)

* More fixes for sleep and clocking stuff on MIMXRT105x

* Fix a couple of inadvertent changes

drivers/tests/TESTS/mbed_drivers/ticker/main.cpp

@@ -185,6 +185,7 @@ void test_multi_ticker(void)
  }
 
  ThisThread::sleep_for(MULTI_TICKER_TIME + extra_wait);
+
  TEST_ASSERT_EQUAL(TICKER_COUNT, multi_counter);
 
  for (int i = 0; i < TICKER_COUNT; i++) {

hal/tests/TESTS/mbed_hal/sleep/main.cpp

@@ -20,6 +20,8 @@
 
 #include "mbed.h"
 
+#include <cinttypes>
+
 #include "utest/utest.h"
 #include "unity/unity.h"
 #include "greentea-client/test_env.h"
@@ -146,7 +148,7 @@ void deepsleep_lpticker_test()
 
  const timestamp_t wakeup_timestamp = lp_ticker_read();
 
- sprintf(info, "Delta ticks: %u, Ticker width: %u, Expected wake up tick: %d, Actual wake up tick: %d, delay ticks: %d, wake up after ticks: %d",
+ sprintf(info, "Delta ticks: %u, Ticker width: %u, Expected wake up tick: %" PRIu32 ", Actual wake up tick: %" PRIu32 ", delay ticks: %d, wake up after ticks: %" PRIu32 "\n",
  us_to_ticks(deepsleep_mode_delta_us, ticker_freq), ticker_width, next_match_timestamp, wakeup_timestamp, us_to_ticks(i, ticker_freq), wakeup_timestamp - start_timestamp);
 
  TEST_ASSERT_MESSAGE(compare_timestamps(us_to_ticks(deepsleep_mode_delta_us, ticker_freq), ticker_width,
@@ -196,7 +198,7 @@ void deepsleep_high_speed_clocks_turned_off_test()
 
  TEST_ASSERT_UINT32_WITHIN(1000, 0, ticks_to_us(us_ticks_diff, us_ticker_freq));
 
- sprintf(info, "Delta ticks: %u, Ticker width: %u, Expected wake up tick: %d, Actual wake up tick: %d",
+ sprintf(info, "Delta ticks: %u, Ticker width: %u, Expected wake up tick: %" PRIu32 ", Actual wake up tick: %d\n",
  us_to_ticks(deepsleep_mode_delta_us, lp_ticker_freq), lp_ticker_width, wakeup_time, lp_ticks_after_sleep);
 
  /* Check if we have woken-up after expected time. */

hal/tests/TESTS/mbed_hal/sleep_manager/main.cpp

@@ -28,7 +28,12 @@
 #error [NOT_SUPPORTED] test not supported
 #else
 
-#define SLEEP_DURATION_US 20000ULL
+#define SLEEP_DURATION_US 50000ULL
+
+// Tolerance for extra sleep time in the deep sleep test.
+// Current leader is the MIMXRT105x, which takes almost 5ms to enter/exit deep sleep.
+#define DEEP_SLEEP_TOLERANCE_US 5000ULL
+
 #define DEEP_SLEEP_TEST_CHECK_WAIT_US 2000
 // As sleep_manager_can_deep_sleep_test_check() is based on wait_ns
 // and wait_ns can be up to 40% slower, use a 50% delta here.
@@ -217,9 +222,12 @@ void test_sleep_auto()
  // 1. current lp_ticker increment,
  // 2. previous us_ticker increment (locked sleep test above)
 
+ const unsigned int deepsleep_tolerance_lp_ticks = us_to_ticks(DEEP_SLEEP_TOLERANCE_US, lp_ticker_info->frequency);
+ const unsigned int deepsleep_tolerance_us_ticks = us_to_ticks(DEEP_SLEEP_TOLERANCE_US, us_ticker_info->frequency);
+
  // us ticker should not have incremented during deep sleep. It should be zero, plus some tolerance for the time to enter deep sleep.
- TEST_ASSERT_UINT64_WITHIN_MESSAGE(sleep_duration_us_ticks / 10ULL, 0, us_diff2, "us ticker sleep time incorrect - perhaps deep sleep mode was not used?");
- TEST_ASSERT_UINT64_WITHIN_MESSAGE(sleep_duration_lp_ticks / 10ULL, sleep_duration_lp_ticks, lp_diff2, "lp ticker sleep time incorrect");
+ TEST_ASSERT_UINT64_WITHIN_MESSAGE(deepsleep_tolerance_us_ticks, 0, us_diff2, "us ticker sleep time incorrect - perhaps deep sleep mode was not used?");
+ TEST_ASSERT_UINT64_WITHIN_MESSAGE(deepsleep_tolerance_lp_ticks, sleep_duration_lp_ticks, lp_diff2, "lp ticker sleep time incorrect");
 
  set_us_ticker_irq_handler(us_ticker_irq_handler_org);
  set_lp_ticker_irq_handler(lp_ticker_irq_handler_org);

targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_MIMXRT105x/clock_config.c

@@ -20,14 +20,13 @@
  *
  */
 
-
 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
 !!GlobalInfo
 product: Clocks v11.0
 processor: MIMXRT1052xxxxB
 package_id: MIMXRT1052DVL6B
 mcu_data: ksdk2_0
-processor_version: 13.0.1
+processor_version: 13.0.2
  * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
 
 #include "clock_config.h"
@@ -46,6 +45,7 @@ processor_version: 13.0.1
  ******************************************************************************/
 void BOARD_InitBootClocks(void)
 {
+ BOARD_ClockOverdrive();
 }
 
 /*******************************************************************************
@@ -66,15 +66,15 @@ name: BOARD_ClockFullSpeed
 - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
 - {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
 - {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz}
-- {id: GPT1_ipg_clk_highfreq.outFreq, value: 66 MHz}
-- {id: GPT2_ipg_clk_highfreq.outFreq, value: 66 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 24 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 24 MHz}
 - {id: IPG_CLK_ROOT.outFreq, value: 132 MHz}
 - {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
-- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
-- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 10 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 2880/77 MHz}
 - {id: LVDS1_CLK.outFreq, value: 1.056 GHz}
 - {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
-- {id: PERCLK_CLK_ROOT.outFreq, value: 66 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 24 MHz}
 - {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
 - {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
 - {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
@@ -89,18 +89,22 @@ name: BOARD_ClockFullSpeed
 - {id: SEMC_CLK_ROOT.outFreq, value: 66 MHz}
 - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
 - {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
-- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 24 MHz}
 - {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
 - {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
 settings:
 - {id: CCM.AHB_PODF.scale, value: '1', locked: true}
 - {id: CCM.ARM_PODF.scale, value: '2', locked: true}
 - {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true}
 - {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL}
-- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
-- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.LPI2C_CLK_PODF.scale, value: '6', locked: true}
+- {id: CCM.LPSPI_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.LPSPI_PODF.scale, value: '7', locked: true}
+- {id: CCM.PERCLK_CLK_SEL.sel, value: XTALOSC24M.OSC_CLK}
+- {id: CCM.PERCLK_PODF.scale, value: '1', locked: true}
 - {id: CCM.SEMC_PODF.scale, value: '8'}
 - {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
+- {id: CCM.UART_CLK_SEL.sel, value: XTALOSC24M.OSC_CLK}
 - {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
 - {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
 - {id: CCM_ANALOG.PLL1_VDIV.scale, value: '44', locked: true}
@@ -194,7 +198,7 @@ void BOARD_ClockFullSpeed(void)
  CLOCK_DisableClock(kCLOCK_Gpt2S);
  CLOCK_DisableClock(kCLOCK_Pit);
  /* Set PERCLK_PODF. */
- CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+ CLOCK_SetDiv(kCLOCK_PerclkDiv, 0);
  /* Disable USDHC1 clock gate. */
  CLOCK_DisableClock(kCLOCK_Usdhc1);
  /* Set USDHC1_PODF. */
@@ -243,9 +247,9 @@ void BOARD_ClockFullSpeed(void)
  CLOCK_DisableClock(kCLOCK_Lpspi3);
  CLOCK_DisableClock(kCLOCK_Lpspi4);
  /* Set LPSPI_PODF. */
- CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+ CLOCK_SetDiv(kCLOCK_LpspiDiv, 6);
  /* Set Lpspi clock source. */
- CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+ CLOCK_SetMux(kCLOCK_LpspiMux, 1);
  /* Disable TRACE clock gate. */
  CLOCK_DisableClock(kCLOCK_Trace);
  /* Set TRACE_PODF. */
@@ -281,7 +285,7 @@ void BOARD_ClockFullSpeed(void)
  CLOCK_DisableClock(kCLOCK_Lpi2c2);
  CLOCK_DisableClock(kCLOCK_Lpi2c3);
  /* Set LPI2C_CLK_PODF. */
- CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+ CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 5);
  /* Set Lpi2c clock source. */
  CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
  /* Disable CAN clock gate. */
@@ -305,7 +309,7 @@ void BOARD_ClockFullSpeed(void)
  /* Set UART_CLK_PODF. */
  CLOCK_SetDiv(kCLOCK_UartDiv, 0);
  /* Set Uart clock source. */
- CLOCK_SetMux(kCLOCK_UartMux, 0);
+ CLOCK_SetMux(kCLOCK_UartMux, 1);
  /* Disable LCDIF clock gate. */
  CLOCK_DisableClock(kCLOCK_LcdPixel);
  /* Set LCDIF_PRED. */
@@ -417,7 +421,7 @@ void BOARD_ClockFullSpeed(void)
  /* Set periph clock2 clock source. */
  CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
  /* Set per clock source. */
- CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+ CLOCK_SetMux(kCLOCK_PerclkMux, 1);
  /* Set lvds1 clock source. */
  CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
  /* Set clock out1 divider. */
@@ -469,6 +473,7 @@ void BOARD_ClockFullSpeed(void)
 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
 !!Configuration
 name: BOARD_ClockOverdrive
+called_from_default_init: true
 outputs:
 - {id: AHB_CLK_ROOT.outFreq, value: 600 MHz}
 - {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
@@ -481,15 +486,15 @@ name: BOARD_ClockOverdrive
 - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
 - {id: FLEXIO2_CLK_ROOT.outFreq, value: 30 MHz}
 - {id: FLEXSPI_CLK_ROOT.outFreq, value: 160 MHz}
-- {id: GPT1_ipg_clk_highfreq.outFreq, value: 75 MHz}
-- {id: GPT2_ipg_clk_highfreq.outFreq, value: 75 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 24 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 24 MHz}
 - {id: IPG_CLK_ROOT.outFreq, value: 150 MHz}
 - {id: LCDIF_CLK_ROOT.outFreq, value: 67.5 MHz}
-- {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
-- {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
+- {id: LPI2C_CLK_ROOT.outFreq, value: 10 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 2880/77 MHz}
 - {id: LVDS1_CLK.outFreq, value: 1.2 GHz}
 - {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
-- {id: PERCLK_CLK_ROOT.outFreq, value: 75 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 24 MHz}
 - {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
 - {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
 - {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
@@ -504,18 +509,22 @@ name: BOARD_ClockOverdrive
 - {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
 - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
 - {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
-- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 24 MHz}
 - {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
 - {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
 settings:
 - {id: CCM.AHB_PODF.scale, value: '1', locked: true}
 - {id: CCM.ARM_PODF.scale, value: '2', locked: true}
 - {id: CCM.FLEXSPI_PODF.scale, value: '3', locked: true}
 - {id: CCM.FLEXSPI_SEL.sel, value: CCM.PLL3_SW_CLK_SEL}
-- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
-- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
+- {id: CCM.LPI2C_CLK_PODF.scale, value: '6', locked: true}
+- {id: CCM.LPSPI_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.LPSPI_PODF.scale, value: '7', locked: true}
+- {id: CCM.PERCLK_CLK_SEL.sel, value: XTALOSC24M.OSC_CLK}
+- {id: CCM.PERCLK_PODF.scale, value: '1', locked: true}
 - {id: CCM.SEMC_PODF.scale, value: '8'}
 - {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
+- {id: CCM.UART_CLK_SEL.sel, value: XTALOSC24M.OSC_CLK}
 - {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
 - {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
 - {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
@@ -615,7 +624,7 @@ void BOARD_ClockOverdrive(void)
  CLOCK_DisableClock(kCLOCK_Gpt2S);
  CLOCK_DisableClock(kCLOCK_Pit);
  /* Set PERCLK_PODF. */
- CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
+ CLOCK_SetDiv(kCLOCK_PerclkDiv, 0);
  /* Disable USDHC1 clock gate. */
  CLOCK_DisableClock(kCLOCK_Usdhc1);
  /* Set USDHC1_PODF. */
@@ -664,9 +673,9 @@ void BOARD_ClockOverdrive(void)
  CLOCK_DisableClock(kCLOCK_Lpspi3);
  CLOCK_DisableClock(kCLOCK_Lpspi4);
  /* Set LPSPI_PODF. */
- CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
+ CLOCK_SetDiv(kCLOCK_LpspiDiv, 6);
  /* Set Lpspi clock source. */
- CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+ CLOCK_SetMux(kCLOCK_LpspiMux, 1);
  /* Disable TRACE clock gate. */
  CLOCK_DisableClock(kCLOCK_Trace);
  /* Set TRACE_PODF. */
@@ -702,7 +711,7 @@ void BOARD_ClockOverdrive(void)
  CLOCK_DisableClock(kCLOCK_Lpi2c2);
  CLOCK_DisableClock(kCLOCK_Lpi2c3);
  /* Set LPI2C_CLK_PODF. */
- CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
+ CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 5);
  /* Set Lpi2c clock source. */
  CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
  /* Disable CAN clock gate. */
@@ -726,7 +735,7 @@ void BOARD_ClockOverdrive(void)
  /* Set UART_CLK_PODF. */
  CLOCK_SetDiv(kCLOCK_UartDiv, 0);
  /* Set Uart clock source. */
- CLOCK_SetMux(kCLOCK_UartMux, 0);
+ CLOCK_SetMux(kCLOCK_UartMux, 1);
  /* Disable LCDIF clock gate. */
  CLOCK_DisableClock(kCLOCK_LcdPixel);
  /* Set LCDIF_PRED. */
@@ -838,7 +847,7 @@ void BOARD_ClockOverdrive(void)
  /* Set periph clock2 clock source. */
  CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
  /* Set per clock source. */
- CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+ CLOCK_SetMux(kCLOCK_PerclkMux, 1);
  /* Set lvds1 clock source. */
  CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
  /* Set clock out1 divider. */
@@ -902,15 +911,15 @@ description: Clocks the MIMRT using the lowest possible power settings (core run
 - {id: FLEXIO1_CLK_ROOT.outFreq, value: 1.5 MHz}
 - {id: FLEXIO2_CLK_ROOT.outFreq, value: 1.5 MHz}
 - {id: FLEXSPI_CLK_ROOT.outFreq, value: 24 MHz}
-- {id: GPT1_ipg_clk_highfreq.outFreq, value: 12 MHz}
-- {id: GPT2_ipg_clk_highfreq.outFreq, value: 12 MHz}
+- {id: GPT1_ipg_clk_highfreq.outFreq, value: 24 MHz}
+- {id: GPT2_ipg_clk_highfreq.outFreq, value: 24 MHz}
 - {id: IPG_CLK_ROOT.outFreq, value: 12 MHz}
 - {id: LCDIF_CLK_ROOT.outFreq, value: 3 MHz}
 - {id: LPI2C_CLK_ROOT.outFreq, value: 3 MHz}
-- {id: LPSPI_CLK_ROOT.outFreq, value: 6 MHz}
+- {id: LPSPI_CLK_ROOT.outFreq, value: 3 MHz}
 - {id: LVDS1_CLK.outFreq, value: 24 MHz}
 - {id: MQS_MCLK.outFreq, value: 3 MHz}
-- {id: PERCLK_CLK_ROOT.outFreq, value: 12 MHz}
+- {id: PERCLK_CLK_ROOT.outFreq, value: 24 MHz}
 - {id: PLL7_MAIN_CLK.outFreq, value: 24 MHz}
 - {id: SAI1_CLK_ROOT.outFreq, value: 3 MHz}
 - {id: SAI1_MCLK1.outFreq, value: 3 MHz}
@@ -925,15 +934,19 @@ description: Clocks the MIMRT using the lowest possible power settings (core run
 - {id: SEMC_CLK_ROOT.outFreq, value: 24 MHz}
 - {id: SPDIF0_CLK_ROOT.outFreq, value: 1.5 MHz}
 - {id: TRACE_CLK_ROOT.outFreq, value: 6 MHz}
-- {id: UART_CLK_ROOT.outFreq, value: 4 MHz}
+- {id: UART_CLK_ROOT.outFreq, value: 24 MHz}
 - {id: USDHC1_CLK_ROOT.outFreq, value: 12 MHz}
 - {id: USDHC2_CLK_ROOT.outFreq, value: 12 MHz}
 settings:
 - {id: CCM.FLEXSPI_PODF.scale, value: '1', locked: true}
 - {id: CCM.IPG_PODF.scale, value: '2', locked: true}
+- {id: CCM.LPSPI_CLK_SEL.sel, value: CCM_ANALOG.PLL3_PFD0_CLK}
+- {id: CCM.LPSPI_PODF.scale, value: '8', locked: true}
+- {id: CCM.PERCLK_CLK_SEL.sel, value: XTALOSC24M.OSC_CLK}
 - {id: CCM.PERIPH_CLK2_SEL.sel, value: XTALOSC24M.OSC_CLK}
 - {id: CCM.PERIPH_CLK_SEL.sel, value: CCM.PERIPH_CLK2_PODF}
 - {id: CCM.SEMC_PODF.scale, value: '1', locked: true}
+- {id: CCM.UART_CLK_SEL.sel, value: XTALOSC24M.OSC_CLK}
 - {id: CCM_ANALOG.PLL2.denom, value: '1'}
 - {id: CCM_ANALOG.PLL2.num, value: '0'}
 - {id: CCM_ANALOG_PLL_ARM_POWERDOWN_CFG, value: 'Yes'}
@@ -1036,9 +1049,9 @@ void BOARD_ClockLowPower(void)
  CLOCK_DisableClock(kCLOCK_Lpspi3);
  CLOCK_DisableClock(kCLOCK_Lpspi4);
  /* Set LPSPI_PODF. */
- CLOCK_SetDiv(kCLOCK_LpspiDiv, 3);
+ CLOCK_SetDiv(kCLOCK_LpspiDiv, 7);
  /* Set Lpspi clock source. */
- CLOCK_SetMux(kCLOCK_LpspiMux, 2);
+ CLOCK_SetMux(kCLOCK_LpspiMux, 1);
  /* Disable TRACE clock gate. */
  CLOCK_DisableClock(kCLOCK_Trace);
  /* Set TRACE_PODF. */
@@ -1098,7 +1111,7 @@ void BOARD_ClockLowPower(void)
  /* Set UART_CLK_PODF. */
  CLOCK_SetDiv(kCLOCK_UartDiv, 0);
  /* Set Uart clock source. */
- CLOCK_SetMux(kCLOCK_UartMux, 0);
+ CLOCK_SetMux(kCLOCK_UartMux, 1);
  /* Disable LCDIF clock gate. */
  CLOCK_DisableClock(kCLOCK_LcdPixel);
  /* Set LCDIF_PRED. */
@@ -1206,7 +1219,7 @@ void BOARD_ClockLowPower(void)
  /* Set periph clock source. */
  CLOCK_SetMux(kCLOCK_PeriphMux, 1);
  /* Set per clock source. */
- CLOCK_SetMux(kCLOCK_PerclkMux, 0);
+ CLOCK_SetMux(kCLOCK_PerclkMux, 1);
  /* Set lvds1 clock source. */
  CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
  /* Set clock out1 divider. */