Few fixes. (#2)

JoseCalero · Jan 10, 2024 · 5a56461 · 5a56461
1 parent 8337662
commit 5a56461
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Showing 4 changed files with 6 additions and 10 deletions.
diff --git a/hw/fpga/constraints/nexys/constraints.xdc b/hw/fpga/constraints/nexys/constraints.xdc
@@ -1 +1 @@
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets x_heep_system_i/pad_ring_i/pad_clk_i/xilinx_iobuf_i/O]
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_i}];
diff --git a/hw/fpga/constraints/nexys/pin_assign.xdc b/hw/fpga/constraints/nexys/pin_assign.xdc
@@ -4,15 +4,13 @@
 
 ## Clock signal
 set_property -dict {PACKAGE_PIN E3 IOSTANDARD LVCMOS33} [get_ports {clk_i}]; #IO_L12P_T1_MRCC_35 Sch=clk100mhz
-create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_i}];
 
 
 set_property -dict {PACKAGE_PIN C12 IOSTANDARD LVCMOS33} [get_ports {rst_i}]; #IO_L3P_T0_DQS_AD1P_15 Sch=cpu_resetn
 
 ## LEDs
-set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {rst_led}];
-set_property -dict {PACKAGE_PIN K15 IOSTANDARD LVCMOS33} [get_ports {clk_out}];
-set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports {clk_led}];
+set_property -dict {PACKAGE_PIN V11 IOSTANDARD LVCMOS33} [get_ports {rst_led_o}];
+set_property -dict {PACKAGE_PIN J13 IOSTANDARD LVCMOS33} [get_ports {clk_led_o}];
 set_property -dict {PACKAGE_PIN N14 IOSTANDARD LVCMOS33} [get_ports {exit_valid_o}];
 set_property -dict {PACKAGE_PIN R18 IOSTANDARD LVCMOS33} [get_ports {exit_value_o}];
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets rst_led_OBUF]

diff --git a/hw/fpga/constraints/pynq-z2/constraints.xdc b/hw/fpga/constraints/pynq-z2/constraints.xdc
@@ -1 +1 @@
-set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets x_heep_system_i/pad_ring_i/pad_clk_i/xilinx_iobuf_i/O]
+create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_i}];
diff --git a/hw/fpga/constraints/pynq-z2/pin_assign.xdc b/hw/fpga/constraints/pynq-z2/pin_assign.xdc
@@ -4,15 +4,13 @@
 
 # Clock signal
 set_property -dict {PACKAGE_PIN H16 IOSTANDARD LVCMOS33} [get_ports clk_i]
-create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_i}];
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets jtag_tck_i_IBUF]
 
 set_property -dict {PACKAGE_PIN L19 IOSTANDARD LVCMOS33} [get_ports rst_i]
 
 # LEDs
-set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports rst_led]
-set_property -dict {PACKAGE_PIN W9 IOSTANDARD LVCMOS33} [get_ports clk_out]
-set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports clk_led]
+set_property -dict {PACKAGE_PIN M14 IOSTANDARD LVCMOS33} [get_ports rst_led_o]
+set_property -dict {PACKAGE_PIN N16 IOSTANDARD LVCMOS33} [get_ports clk_led_o]
 set_property -dict {PACKAGE_PIN R14 IOSTANDARD LVCMOS33} [get_ports exit_valid_o]
 set_property -dict {PACKAGE_PIN P14 IOSTANDARD LVCMOS33} [get_ports exit_value_o]
 set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets rst_led_OBUF]
Original file line number	Diff line number	Diff line change
		@@ -1 +1 @@
		set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets x_heep_system_i/pad_ring_i/pad_clk_i/xilinx_iobuf_i/O]
		create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports {clk_i}];