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Upgrade sim to generate clocks in HDL #174

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JulianKemmerer opened this issue Aug 26, 2023 · 0 comments
Open

Upgrade sim to generate clocks in HDL #174

JulianKemmerer opened this issue Aug 26, 2023 · 0 comments
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enhancement New feature or request

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@JulianKemmerer
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This also makes it easier to support multiple clocks

For Verilator first probably...IIUC this needs newer Verilator than have worked with before

Generate a generic testbench module with clock gen processes that instantiates the top when --sim ?
@JulianKemmerer JulianKemmerer added the enhancement New feature or request label Aug 26, 2023
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