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52 Open 79 Closed
52 Open 79 Closed
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Issues list

Allow __vhdl__ literal to have autopipeline IO regs added enhancement New feature or request
#273 opened Nov 16, 2024 by JulianKemmerer
Add DO_PNR support for tools that support it enhancement New feature or request good first issue Good for newcomers
#272 opened Nov 16, 2024 by JulianKemmerer
Fix how AST nodes are identified uniquely
#267 opened Nov 16, 2024 by JulianKemmerer
Aesthetic VHDL and C code gen fixes enhancement New feature or request good first issue Good for newcomers
#246 opened Nov 16, 2024 by JulianKemmerer
Implement built in fixed point types like was done for floating point
#242 opened Nov 16, 2024 by JulianKemmerer
Remove old WIRE macro/funcs from generated code
#239 opened Nov 16, 2024 by JulianKemmerer
No Modulo / Remainder Operator "%" for integer types
#202 opened Jul 2, 2024 by Paulo-D2000
@JulianKemmerer
2
Built in RAMs render uint0_t address for 1-element arrays bug Something isn't working good first issue Good for newcomers
#197 opened Jun 10, 2024 by JulianKemmerer
1
FEEDBACK wires need a default assignment in code bug Something isn't working
#192 opened Mar 17, 2024 by JulianKemmerer
1
Change output directory structure enhancement New feature or request
#183 opened Nov 28, 2023 by JulianKemmerer
Support full C syntax for invoking derived FSMs enhancement New feature or request
#180 opened Sep 17, 2023 by JulianKemmerer
Allow operator overloading to work with derived FSM implementations enhancement New feature or request
#179 opened Sep 17, 2023 by JulianKemmerer
Fix operator overloading to allow use of built in operator in overload bug Something isn't working
#178 opened Sep 17, 2023 by JulianKemmerer
Setup Verilator for multiple clock domain simulations enhancement New feature or request
#176 opened Sep 16, 2023 by JulianKemmerer
Autopipelining that adds IO regs to functions w/ global wires is broken bug Something isn't working
#175 opened Aug 27, 2023 by JulianKemmerer
1
Upgrade sim to generate clocks in HDL enhancement New feature or request
#174 opened Aug 26, 2023 by JulianKemmerer
Convert sync integer ratio clock crossing c code gen to define struct instead of using fixed size array types enhancement New feature or request
#171 opened Jul 4, 2023 by JulianKemmerer
Enums with shared literal names can cause VHDL syntax errors bug Something isn't working
#168 opened May 27, 2023 by JulianKemmerer
Only 'cpp' for C preprocessing is supported now enhancement New feature or request
#166 opened Feb 15, 2023 by JulianKemmerer
1
Derived FSM style functions have lots of room for optimizations enhancement New feature or request
#163 opened Feb 7, 2023 by JulianKemmerer
2
Union support enhancement New feature or request
#162 opened Feb 6, 2023 by JulianKemmerer
1
Global variables of compound types cannot be driven from multiple main functions enhancement New feature or request
#148 opened Nov 23, 2022 by JulianKemmerer
Static local variables cannot be declared inside IFs bug Something isn't working
#146 opened Nov 5, 2022 by JulianKemmerer
FIFO_FWFT implementation causes output to pause unexpectedly long after flow control assertion enhancement New feature or request
#142 opened Oct 31, 2022 by JulianKemmerer
2
Loop iterators must be declared outside of the loop bug Something isn't working
#139 opened Oct 28, 2022 by JulianKemmerer
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