Autopipelining that adds IO regs to functions w/ global wires is broken

[JulianKemmerer]

if have ex.

void some_func()
{
    out = the_pipeline_func(in);
}

where in and out are global wires - then, if some_func is selected for having IO registers added to meet timing - the design will break - will get a VHDL syntax error and synth faills.

Missing logic for registering (non volatile) global wires.

Work around for now with ex. #pragma FUNC_NO_ADD_IO_REGS some_func to stop func from getting these broken IO regs added...

[JulianKemmerer]

Generally also want to make sure that the reasoning behind how reads and writes to globals behave around pipelineable logic makes sense ... read in first stage, written from first available stage? what about writing from last stage of pipeline always?