Move to MPW8

Makefile

@@ -24,8 +24,8 @@ SIM?=RTL
 CARAVEL_LITE?=1
 
 # PDK switch varient
-#export PDK?=sky130A
-export PDK?=gf180mcuC
+export PDK?=sky130A
+#export PDK?=gf180mcuC
 export PDKPATH?=$(PDK_ROOT)/$(PDK)
 
 
@@ -111,7 +111,7 @@ patch_mcw:
 	cp -rf ./mgmt_core_wrapper_patch/* ./mgmt_core_wrapper
 
 .PHONY: setup
-setup: install check-env install_mcw patch_mcw openlane pdk-with-volare setup-timing-scripts
+setup: install check-env install_mcw openlane pdk-with-volare setup-timing-scripts
 	$(print-debug)
 
 # Openlane

README.md

@@ -104,7 +104,7 @@ export PDK_ROOT=$project_folder/dependencies/pdks
 export CARAVEL_ROOT=$design_folder/caravel
 export PRECHECK_ROOT=$project_folder/precheck
 
-export PDK=gf180mcuC
+export PDK=sky130A
 
 export PATH="$HOMEDIR.local/bin:$PATH"
 

openlane/step_motor_controller/config.json

@@ -0,0 +1,47 @@
+{
+    "DESIGN_NAME": "step_motor_controller",
+    "DESIGN_IS_CORE": 0,
+    "VERILOG_FILES": ["dir::../../verilog/rtl/step_motor_controller.v", "dir::../../verilog/rtl/prescaler.v"],
+    "SYNTH_PARAMETERS": ["PSIZE=20, DSIZE=20"],
+    "SYNTH_BUFFERING": 1,
+    "CLOCK_PORT": "clk",
+    "CLOCK_NET": "clk",
+    "FP_SIZING": "absolute",
+    "DIE_AREA": "0 0 400 350",
+    "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
+    "PL_BASIC_PLACEMENT": 0,
+    "PL_TARGET_DENSITY": 0.55,
+    "PL_TIME_DRIVEN": 1,
+    "VDD_NETS": ["vdd"],
+    "GND_NETS": ["vss"],
+    "DIODE_INSERTION_STRATEGY": 4,
+    "RUN_CVC": 1,
+    "pdk::sky130*": {
+        "FP_CORE_UTIL": 45,
+        "RT_MAX_LAYER": "met4",
+        "scl::sky130_fd_sc_hd": {
+            "CLOCK_PERIOD": 10
+        },
+        "scl::sky130_fd_sc_hdll": {
+            "CLOCK_PERIOD": 10
+        },
+        "scl::sky130_fd_sc_hs": {
+            "CLOCK_PERIOD": 8
+        },
+        "scl::sky130_fd_sc_ls": {
+            "CLOCK_PERIOD": 10,
+            "SYNTH_MAX_FANOUT": 5
+        },
+        "scl::sky130_fd_sc_ms": {
+            "CLOCK_PERIOD": 10
+        }
+    },
+    "pdk::gf180mcuC": {
+        "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
+        "CLOCK_PERIOD": 24.0,
+        "FP_CORE_UTIL": 40,
+        "RT_MAX_LAYER": "Metal4",
+        "SYNTH_MAX_FANOUT": 4,
+        "PL_TARGET_DENSITY": 0.45
+    }
+}

openlane/step_motor_controller/config.tcl

@@ -0,0 +1,62 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+# SPDX-License-Identifier: Apache-2.0
+
+set ::env(PDK) "sky130A"
+#set ::env(STD_CELL_LIBRARY) "gf180mcu_fd_sc_mcu7t5v0"
+
+set ::env(DESIGN_NAME) step_motor_controller
+
+set ::env(VERILOG_FILES) "\
+	$::env(CARAVEL_ROOT)/verilog/rtl/defines.v \
+	$::env(DESIGN_DIR)/../../verilog/rtl/defines.v \
+	$::env(DESIGN_DIR)/../../verilog/rtl/prescaler.v \
+	$::env(DESIGN_DIR)/../../verilog/rtl/step_motor_controller.v "
+
+set ::env(DESIGN_IS_CORE) 0
+
+set ::env(CLOCK_PORT) "clk"
+set ::env(CLOCK_NET) "clk"
+set ::env(CLOCK_PERIOD) "15.0"
+
+set ::env(FP_SIZING) absolute
+set ::env(DIE_AREA) "0 0 500 400"
+
+set ::env(FP_PIN_ORDER_CFG) $::env(DESIGN_DIR)/pin_order.cfg
+
+set ::env(PL_BASIC_PLACEMENT) 0
+set ::env(PL_TARGET_DENSITY) 0.45
+set ::env(PL_TIME_DRIVEN) 1
+
+set ::env(FP_CORE_UTIL) 40
+
+set ::env(SYNTH_STRATEGY) "DELAY 3"
+set ::env(SYNTH_MAX_FANOUT) 4
+set ::env(SYNTH_BUFFERING) 1
+
+# Maximum layer used for routing is metal 4.
+# This is because this macro will be inserted in a top level (user_project_wrapper) 
+# where the PDN is planned on metal 5. So, to avoid having shorts between routes
+# in this macro and the top level metal 5 stripes, we have to restrict routes to metal4.  
+# 
+set ::env(RT_MAX_LAYER) {Metal4}
+
+# You can draw more power domains if you need to 
+set ::env(VDD_NETS) [list {vdd}]
+set ::env(GND_NETS) [list {vss}]
+
+set ::env(DIODE_INSERTION_STRATEGY) 4
+
+# If you're going to use multiple power domains, then disable cvc run.
+set ::env(RUN_CVC) 1

openlane/step_motor_controller/pin_order.cfg

@@ -0,0 +1,117 @@
+#BUS_SORT
+
+#S
+rst_n
+clk
+wbs_cyc_i
+wbs_stb_i
+wbs_we_i
+wbs_ack_o
+wbs_sel_i\[3\]
+wbs_sel_i\[2\]
+wbs_sel_i\[1\]
+wbs_sel_i\[0\]
+
+wbs_adr_i\[31\]
+wbs_adr_i\[30\]
+wbs_adr_i\[29\]
+wbs_adr_i\[28\]
+wbs_adr_i\[27\]
+wbs_adr_i\[26\]
+wbs_adr_i\[25\]
+wbs_adr_i\[24\]
+wbs_adr_i\[23\]
+wbs_adr_i\[22\]
+wbs_adr_i\[21\]
+wbs_adr_i\[20\]
+wbs_adr_i\[19\]
+wbs_adr_i\[18\]
+wbs_adr_i\[17\]
+wbs_adr_i\[16\]
+wbs_adr_i\[15\]
+wbs_adr_i\[14\]
+wbs_adr_i\[13\]
+wbs_adr_i\[12\]
+wbs_adr_i\[11\]
+wbs_adr_i\[10\]
+wbs_adr_i\[9\]
+wbs_adr_i\[8\]
+wbs_adr_i\[7\]
+wbs_adr_i\[6\]
+wbs_adr_i\[5\]
+wbs_adr_i\[4\]
+wbs_adr_i\[3\]
+wbs_adr_i\[2\]
+wbs_adr_i\[1\]
+wbs_adr_i\[0\]
+
+wbs_dat_o\[31\]
+wbs_dat_i\[31\]
+wbs_dat_o\[30\]
+wbs_dat_i\[30\]
+wbs_dat_o\[29\]
+wbs_dat_i\[29\]
+wbs_dat_o\[28\]
+wbs_dat_i\[28\]
+wbs_dat_o\[27\]
+wbs_dat_i\[27\]
+wbs_dat_o\[26\]
+wbs_dat_i\[26\]
+wbs_dat_o\[25\]
+wbs_dat_i\[25\]
+wbs_dat_o\[24\]
+wbs_dat_i\[24\]
+wbs_dat_o\[23\]
+wbs_dat_i\[23\]
+wbs_dat_o\[22\]
+wbs_dat_i\[22\]
+wbs_dat_o\[21\]
+wbs_dat_i\[21\]
+wbs_dat_o\[20\]
+wbs_dat_i\[20\]
+wbs_dat_o\[19\]
+wbs_dat_i\[19\]
+wbs_dat_o\[18\]
+wbs_dat_i\[18\]
+wbs_dat_o\[17\]
+wbs_dat_i\[17\]
+wbs_dat_o\[16\]
+wbs_dat_i\[16\]
+wbs_dat_o\[15\]
+wbs_dat_i\[15\]
+wbs_dat_o\[14\]
+wbs_dat_i\[14\]
+wbs_dat_o\[13\]
+wbs_dat_i\[13\]
+wbs_dat_o\[12\]
+wbs_dat_i\[12\]
+wbs_dat_o\[11\]
+wbs_dat_i\[11\]
+wbs_dat_o\[10\]
+wbs_dat_i\[10\]
+wbs_dat_o\[9\]
+wbs_dat_i\[9\]
+wbs_dat_o\[8\]
+wbs_dat_i\[8\]
+wbs_dat_o\[7\]
+wbs_dat_i\[7\]
+wbs_dat_o\[6\]
+wbs_dat_i\[6\]
+wbs_dat_o\[5\]
+wbs_dat_i\[5\]
+wbs_dat_o\[4\]
+wbs_dat_i\[4\]
+wbs_dat_o\[3\]
+wbs_dat_i\[3\]
+wbs_dat_o\[2\]
+wbs_dat_i\[2\]
+wbs_dat_o\[1\]
+wbs_dat_i\[1\]
+wbs_dat_o\[0\]
+wbs_dat_i\[0\]
+
+#N
+motor_a1
+motor_a2
+motor_b1
+motor_b2

openlane/user_proj_example/config.tcl

@@ -13,8 +13,8 @@
 # limitations under the License.
 # SPDX-License-Identifier: Apache-2.0
 
-set ::env(PDK) "gf180mcuC"
-set ::env(STD_CELL_LIBRARY) "gf180mcu_fd_sc_mcu7t5v0"
+set ::env(PDK) "sky130A"
+#set ::env(STD_CELL_LIBRARY) "gf180mcu_fd_sc_mcu7t5v0"
 
 set ::env(DESIGN_NAME) user_proj_example
 

openlane/user_project_wrapper/config.tcl

@@ -16,8 +16,8 @@
 # Base Configurations. Don't Touch
 # section begin
 
-set ::env(PDK) "gf180mcuC"
-set ::env(STD_CELL_LIBRARY) "gf180mcu_fd_sc_mcu7t5v0"
+set ::env(PDK) "sky130A"
+#set ::env(STD_CELL_LIBRARY) "gf180mcu_fd_sc_mcu7t5v0"
 
 # YOU CAN CHANGE ANY VARIABLES DEFINED IN THE DEFAULT WRAPPER CFGS BY OVERRIDING THEM IN THIS CONFIG.TCL
 source $::env(DESIGN_DIR)/fixed_dont_change/default_wrapper_cfgs.tcl