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VHDL -> Verilog
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@Jwiggiff
Jwiggiff committed Feb 13, 2024
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2 changes: 1 addition & 1 deletion src/_data/skills.yml
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Expand Up @@ -9,7 +9,7 @@ Languages:
- C
- Java
- Assembly
- VHDL
- Verilog
Frameworks:
- NodeJS
- React
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