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Pipeline CPU

A pipeline cpu based on MIPS instruction set

  • This is a project created by quartus. The *.v files is the vital Verilog code, and *.vt files under modelsim folder is for simulation.
  • The cpu supports 20 instructions which covers most of vital arithmetic instructions and branch instructions.
  • 5-segment pipeline with forwarding unit, static branch prediction, cache, and exception handler entry.

Teamwork

  • The project is done by the team of 2.
  • I'm in charge of 3 of 5 pipeline segments, ALU, register file, barrel shifter, controller, memory, and exception handler entry.

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MIPS pipeline CPU(32bit)

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  • Verilog 60.3%
  • VHDL 25.0%
  • HTML 9.1%
  • Stata 3.2%
  • Python 2.4%