Transplant μC/OS II Operating System on 89-instructions MIPS dynamic pipeline CPU
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Realized 89 MIPS CPU, GPIO, UART serial port on Digilent Nexys4 FPGA board, and realized DDR2 reading and writing by MIG, SPI FLASH reading, and seven-segment digital tube, and used Wishbone B2 to connect all modules
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Modified the μC/OS II system, compiled it using the Ubuntu cross-compilation environment, coded it to the flash, and achieved serial port output after running
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For more information, refer to CPU report and OS report.
- Vivado 2016.2
- Digilent Nexys 4 DDR FPGA board
- Mars 4.5: Mips Assembly and Runtime Simulator
- Include all the files in code directory.
- Use Vivado to synthesis, implementation, generate bitstream and program to board.
- Configure the spi flash data and write it to the binary program file of the μC/OS II operating system. You need to specify the Configuration file.
- Serial Port Result
- Enable serial port debugging, set the baud rate to 19200 BPS, data bit to 8, no parity bit, and stop bit to 1. Run the bit down the board to observe the serial communication
- I use SSCOM to listen for signals over the serial port, but any serial debugger will work
- Digital tube GPIO output, sw[3:0]=6, check gpio output.
- We provide pre-compiled operating system files here. If you need to
modify, you can also follow the steps below
- Compile the bootloader
- Compile μC/OSII system
- Configure the spi flash data and write it to the binary program file of the μC/OS II operating system. You need to specify the Configuration file.
- Serial Port Result
- Opens the serial port debugging, sets the baud rate to 19200 BPS, 8 data bits, no parity bits, and 1 stop bit. Run the bit down the board to observe the serial communication
- By uart, enter the first operator '5', the operator '-', and the second operator '2' in order. The run ends when the final result is obtained.
- You can also try other operators.
- Digital tube GPIO output, sw[3:0]=6, check gpio output.