sap-computer

The goal of this project is to model the SAP (Simple As Possible) Computer in "Digital Computer Electronics" (Malvino, Brown) in gate-level SystemVerilog. The design will involve a bottoms-up approach beginning with gate-level models of D and JK Flip-Flops. Behavioral models for all designs will be included to simulate against the gate-level models. I will be compiling the HDL code with iverilog and simulating with GTKWave.

Useful links:

https://books.google.com/books/about/Digital_Computer_Electronics.html?id=1QaMPwAACAAJ&source=kp_book_description

https://github.com/steveicarus/iverilog

https://gtkwave.sourceforge.net/