Translate Intel FPGA bank_bits memory attribute

https://github.com/KhronosGroup/SPIRV-Registry/blob/master/extensions/INTEL/SPV_INTEL_fpga_memory_attributes.asciidoc
KhronosGroup · Dec 26, 2019 · 3fdc1a5 · 3fdc1a5
1 parent 1bf22f1
commit 3fdc1a5
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Showing 11 changed files with 152 additions and 16 deletions.
diff --git a/lib/SPIRV/SPIRVReader.cpp b/lib/SPIRV/SPIRVReader.cpp
@@ -2807,6 +2807,14 @@ void generateIntelFPGAAnnotation(const SPIRVEntry *E,
       Out << ":" << Str;
     Out << '}';
   }
+  if (E->hasDecorate(DecorationBankBitsINTEL)) {
+    Out << "{bank_bits:";
+    auto Literals = E->getDecorationLiterals(DecorationBankBitsINTEL);
+    for (size_t I = 0; I < Literals.size() - 1; ++I) {
+      Out << Literals[I] << ",";
+    }
+    Out << Literals[Literals.size() - 1] << '}';
+  }
   if (E->hasDecorate(DecorationUserSemantic))
     Out << E->getDecorationStringLiteral(DecorationUserSemantic).front();
 }
@@ -2848,6 +2856,15 @@ void generateIntelFPGAAnnotationForStructMember(
       Out << ":" << Str;
     Out << '}';
   }
+  if (E->hasMemberDecorate(DecorationBankBitsINTEL, 0, MemberNumber)) {
+    Out << "{bank_bits:";
+    auto Literals =
+        E->getMemberDecorationLiterals(DecorationBankBitsINTEL, MemberNumber);
+    for (size_t I = 0; I < Literals.size() - 1; ++I) {
+      Out << Literals[I] << ",";
+    }
+    Out << Literals[Literals.size() - 1] << '}';
+  }
 
   if (E->hasMemberDecorate(DecorationUserSemantic, 0, MemberNumber))
     Out << E->getMemberDecorationStringLiteral(DecorationUserSemantic,

diff --git a/lib/SPIRV/SPIRVWriter.cpp b/lib/SPIRV/SPIRVWriter.cpp
@@ -1196,6 +1196,7 @@ tryParseIntelFPGAAnnotationString(StringRef AnnotatedCode) {
                 .Case("bankwidth", DecorationBankwidthINTEL)
                 .Case("max_private_copies", DecorationMaxPrivateCopiesINTEL)
                 .Case("max_replicates", DecorationMaxReplicatesINTEL)
+                .Case("bank_bits", DecorationBankBitsINTEL)
                 .Case("merge", DecorationMergeINTEL)
                 .Default(DecorationUserSemantic);
       if (Dec == DecorationUserSemantic)
@@ -1236,6 +1237,18 @@ void addIntelFPGADecorations(
       E->addDecorate(
           new SPIRVDecorateMergeINTELAttr(E, Name.str(), Direction.str()));
     } break;
+    case DecorationBankBitsINTEL: {
+      SmallVector<StringRef, 1> A;
+      StringRef(I.second).split(A, ',');
+      std::vector<SPIRVWord> Bits(A.size());
+      SPIRVWord Result;
+      for (size_t i = 0; i < A.size(); ++i) {
+        Result = 0;
+        A[i].getAsInteger(10, Result);
+        Bits[i] = Result;
+      }
+      E->addDecorate(new SPIRVDecorateBankBitsINTELAttr(E, Bits));
+    } break;
     case DecorationRegisterINTEL:
     case DecorationSinglepumpINTEL:
     case DecorationDoublepumpINTEL:
@@ -1286,6 +1299,19 @@ void addIntelFPGADecorationsForStructMember(
       E->addMemberDecorate(new SPIRVMemberDecorateMergeINTELAttr(
           E, MemberNumber, Name.str(), Direction.str()));
     } break;
+    case DecorationBankBitsINTEL: {
+      SmallVector<StringRef, 1> A;
+      StringRef(I.second).split(A, ',');
+      std::vector<SPIRVWord> Bits(A.size());
+      SPIRVWord Result;
+      for (size_t i = 0; i < A.size(); ++i) {
+        Result = 0;
+        A[i].getAsInteger(10, Result);
+        Bits[i] = Result;
+      }
+      E->addMemberDecorate(
+          new SPIRVMemberDecorateBankBitsINTELAttr(E, MemberNumber, Bits));
+    } break;
     case DecorationRegisterINTEL:
     case DecorationSinglepumpINTEL:
     case DecorationDoublepumpINTEL:

diff --git a/lib/SPIRV/libSPIRV/SPIRVDecorate.h b/lib/SPIRV/libSPIRV/SPIRVDecorate.h
@@ -152,6 +152,7 @@ class SPIRVDecorate : public SPIRVDecorateGeneric {
     case DecorationMaxReplicatesINTEL:
     case DecorationSimpleDualPortINTEL:
     case DecorationMergeINTEL:
+    case DecorationBankBitsINTEL:
       return getSet(ExtensionID::SPV_INTEL_fpga_memory_attributes);
     case DecorationReferencedIndirectlyINTEL:
       return getSet(ExtensionID::SPV_INTEL_function_pointers);
@@ -248,6 +249,7 @@ class SPIRVMemberDecorate : public SPIRVDecorateGeneric {
     case DecorationMaxReplicatesINTEL:
     case DecorationSimpleDualPortINTEL:
     case DecorationMergeINTEL:
+    case DecorationBankBitsINTEL:
       return getSet(ExtensionID::SPV_INTEL_fpga_memory_attributes);
     default:
       return SPIRVExtSet();
@@ -448,6 +450,19 @@ class SPIRVDecorateMergeINTELAttr : public SPIRVDecorate {
   }
 };
 
+class SPIRVDecorateBankBitsINTELAttr : public SPIRVDecorate {
+public:
+  // Complete constructor for BankBitsINTEL decoration
+  SPIRVDecorateBankBitsINTELAttr(SPIRVEntry *TheTarget,
+                                 const std::vector<SPIRVWord> &TheBits)
+      : SPIRVDecorate(DecorationBankBitsINTEL, TheTarget) {
+    for (auto &I : TheBits) {
+      Literals.push_back(I);
+    }
+    WordCount += Literals.size();
+  }
+};
+
 template <Decoration D>
 class SPIRVMemberDecorateStrAttrBase : public SPIRVMemberDecorate {
 public:
@@ -500,6 +515,20 @@ class SPIRVMemberDecorateMergeINTELAttr : public SPIRVMemberDecorate {
   }
 };
 
+class SPIRVMemberDecorateBankBitsINTELAttr : public SPIRVMemberDecorate {
+public:
+  // Complete constructor for BankBitsINTEL decoration
+  SPIRVMemberDecorateBankBitsINTELAttr(SPIRVEntry *TheTarget,
+                                       SPIRVWord MemberNumber,
+                                       const std::vector<SPIRVWord> &TheBits)
+      : SPIRVMemberDecorate(DecorationBankBitsINTEL, MemberNumber, TheTarget) {
+    for (auto &I : TheBits) {
+      Literals.push_back(I);
+    }
+    WordCount += Literals.size();
+  }
+};
+
 } // namespace SPIRV
 
 #endif // SPIRV_LIBSPIRV_SPIRVDECORATE_H
diff --git a/lib/SPIRV/libSPIRV/SPIRVEntry.cpp b/lib/SPIRV/libSPIRV/SPIRVEntry.cpp
@@ -354,6 +354,25 @@ SPIRVEntry::getMemberDecorationStringLiteral(Decoration Kind,
   return getVecString(Loc->second->getVecLiteral());
 }
 
+std::vector<SPIRVWord>
+SPIRVEntry::getDecorationLiterals(Decoration Kind) const {
+  auto Loc = Decorates.find(Kind);
+  if (Loc == Decorates.end())
+    return {};
+
+  return (Loc->second->getVecLiteral());
+}
+
+std::vector<SPIRVWord>
+SPIRVEntry::getMemberDecorationLiterals(Decoration Kind,
+                                        SPIRVWord MemberNumber) const {
+  auto Loc = MemberDecorates.find({MemberNumber, Kind});
+  if (Loc == MemberDecorates.end())
+    return {};
+
+  return (Loc->second->getVecLiteral());
+}
+
 // Get literals of all decorations of Kind at Index.
 std::set<SPIRVWord> SPIRVEntry::getDecorate(Decoration Kind,
                                             size_t Index) const {

diff --git a/lib/SPIRV/libSPIRV/SPIRVEntry.h b/lib/SPIRV/libSPIRV/SPIRVEntry.h
@@ -296,6 +296,9 @@ class SPIRVEntry {
   bool hasMemberDecorate(Decoration Kind, size_t Index = 0,
                          SPIRVWord MemberNumber = 0,
                          SPIRVWord *Result = 0) const;
+  std::vector<SPIRVWord> getDecorationLiterals(Decoration Kind) const;
+  std::vector<SPIRVWord>
+  getMemberDecorationLiterals(Decoration Kind, SPIRVWord MemberNumber) const;
   std::vector<std::string> getDecorationStringLiteral(Decoration Kind) const;
   std::vector<std::string>
   getMemberDecorationStringLiteral(Decoration Kind,

diff --git a/lib/SPIRV/libSPIRV/SPIRVEnum.h b/lib/SPIRV/libSPIRV/SPIRVEnum.h
@@ -362,6 +362,7 @@ template <> inline void SPIRVMap<Decoration, SPIRVCapVec>::init() {
   ADD_VEC_INIT(DecorationSimpleDualPortINTEL,
                {CapabilityFPGAMemoryAttributesINTEL});
   ADD_VEC_INIT(DecorationMergeINTEL, {CapabilityFPGAMemoryAttributesINTEL});
+  ADD_VEC_INIT(DecorationBankBitsINTEL, {CapabilityFPGAMemoryAttributesINTEL});
   ADD_VEC_INIT(DecorationReferencedIndirectlyINTEL,
                {CapabilityIndirectReferencesINTEL});
 }

diff --git a/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h b/lib/SPIRV/libSPIRV/SPIRVIsValidEnum.h
@@ -408,6 +408,7 @@ inline bool isValid(spv::Decoration V) {
   case DecorationMaxPrivateCopiesINTEL:
   case DecorationSinglepumpINTEL:
   case DecorationDoublepumpINTEL:
+  case DecorationBankBitsINTEL:
   case DecorationReferencedIndirectlyINTEL:
     return true;
   default:

diff --git a/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h b/lib/SPIRV/libSPIRV/SPIRVNameMapEnum.h
@@ -345,6 +345,7 @@ template <> inline void SPIRVMap<Decoration, std::string>::init() {
   add(DecorationMaxReplicatesINTEL, "MaxReplicatesINTEL");
   add(DecorationSimpleDualPortINTEL, "SimpleDualPortINTEL");
   add(DecorationMergeINTEL, "MergeINTEL");
+  add(DecorationBankBitsINTEL, "BankBitsINTEL");
   add(DecorationReferencedIndirectlyINTEL, "ReferencedIndirectlyINTEL");
 }
 SPIRV_DEF_NAMEMAP(Decoration, SPIRVDecorationNameMap)

diff --git a/lib/SPIRV/libSPIRV/spirv.hpp b/lib/SPIRV/libSPIRV/spirv.hpp
@@ -404,6 +404,7 @@ enum Decoration {
     DecorationMaxReplicatesINTEL = 5832,
     DecorationSimpleDualPortINTEL = 5833,
     DecorationMergeINTEL = 5834,
+    DecorationBankBitsINTEL = 5835,
     DecorationMax = 0x7fffffff,
 };
 

diff --git a/test/IntelFPGAMemoryAttributes.ll b/test/IntelFPGAMemoryAttributes.ll
@@ -25,6 +25,7 @@
 ; CHECK-SPIRV: Decorate {{[0-9]+}} MaxReplicatesINTEL 2
 ; CHECK-SPIRV: Decorate {{[0-9]+}} SimpleDualPortINTEL
 ; CHECK-SPIRV: Decorate {{[0-9]+}} MergeINTEL "foo" "depth"
+; CHECK-SPIRV: Decorate {{[0-9]+}} BankBitsINTEL 2 1 0
 
 target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
 target triple = "spir64-unknown-linux"
@@ -42,7 +43,8 @@ target triple = "spir64-unknown-linux"
 ; CHECK-LLVM: [[STR8:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{merge:foo:depth}
 ; CHECK-LLVM: [[STR9:@[0-9_.]+]] = {{.*}}{max_replicates:2}
 ; CHECK-LLVM: [[STR10:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{simple_dual_port:1}
-; CHECK-LLVM: [[STR11:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{numbanks:2}
+; CHECK-LLVM: [[STR11:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{numbanks:8}{bank_bits:2,1,0}
+; CHECK-LLVM: [[STR12:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{numbanks:2}
 @.str = private unnamed_addr constant [29 x i8] c"{memory:DEFAULT}{numbanks:4}\00", section "llvm.metadata"
 @.str.1 = private unnamed_addr constant [13 x i8] c"test_var.cpp\00", section "llvm.metadata"
 @.str.2 = private unnamed_addr constant [13 x i8] c"{register:1}\00", section "llvm.metadata"
@@ -54,7 +56,8 @@ target triple = "spir64-unknown-linux"
 @.str.8 = private unnamed_addr constant [34 x i8] c"{memory:DEFAULT}{merge:foo:depth}\00", section "llvm.metadata"
 @.str.9 = private unnamed_addr constant [19 x i8] c"{max_replicates:2}\00", section "llvm.metadata"
 @.str.10 = private unnamed_addr constant [37 x i8] c"{memory:DEFAULT}{simple_dual_port:1}\00", section "llvm.metadata"
-@.str.11 = private unnamed_addr constant [29 x i8] c"{memory:DEFAULT}{numbanks:2}\00", section "llvm.metadata"
+@.str.11 = private unnamed_addr constant [46 x i8] c"{memory:DEFAULT}{numbanks:8}{bank_bits:2,1,0}\00", section "llvm.metadata"
+@.str.12 = private unnamed_addr constant [29 x i8] c"{memory:DEFAULT}{numbanks:2}\00", section "llvm.metadata"
 
 ; Function Attrs: nounwind
 define spir_kernel void @_ZTSZ4mainE15kernel_function() #0 !kernel_arg_addr_space !4 !kernel_arg_access_qual !4 !kernel_arg_type !4 !kernel_arg_base_type !4 !kernel_arg_type_qual !4 {
@@ -98,6 +101,7 @@ entry:
   %var_eight = alloca i32, align 4
   %var_nine = alloca i32, align 4
   %var_ten = alloca i32, align 4
+  %var_eleven = alloca i32, align 4
   %0 = bitcast i32* %var_one to i8*
   call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #4
   %var_one1 = bitcast i32* %var_one to i8*
@@ -146,25 +150,32 @@ entry:
   %var_ten10 = bitcast i32* %var_ten to i8*
   ; CHECK-LLVM: call void @llvm.var.annotation(i8* [[VAR10:%[a-zA-Z0-9_]+]], i8* getelementptr inbounds ([37 x i8], [37 x i8]* [[STR10]], i32 0, i32 0), i8* undef, i32 undef)
   call void @llvm.var.annotation(i8* %var_ten10, i8* getelementptr inbounds ([37 x i8], [37 x i8]* @.str.10, i32 0, i32 0), i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str.1, i32 0, i32 0), i32 11)
-  %9 = bitcast i32* %var_ten to i8*
-  call void @llvm.lifetime.end.p0i8(i64 4, i8* %9) #4
-  %10 = bitcast i32* %var_nine to i8*
+  %9 = bitcast i32* %var_eleven to i8*
+  call void @llvm.lifetime.start.p0i8(i64 4, i8* %9) #4
+  %var_eleven11 = bitcast i32* %var_eleven to i8*
+  ; CHECK-LLVM: call void @llvm.var.annotation(i8* [[VAR11:%[a-zA-Z0-9_]+]], i8* getelementptr inbounds ([46 x i8], [46 x i8]* [[STR11]], i32 0, i32 0), i8* undef, i32 undef)
+  call void @llvm.var.annotation(i8* %var_eleven11, i8* getelementptr inbounds ([46 x i8], [46 x i8]* @.str.11, i32 0, i32 0), i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str.1, i32 0, i32 0), i32 12)
+  %10 = bitcast i32* %var_eleven to i8*
   call void @llvm.lifetime.end.p0i8(i64 4, i8* %10) #4
-  %11 = bitcast i32* %var_eight to i8*
+  %11 = bitcast i32* %var_ten to i8*
   call void @llvm.lifetime.end.p0i8(i64 4, i8* %11) #4
-  %12 = bitcast i32* %var_seven to i8*
+  %12 = bitcast i32* %var_nine to i8*
   call void @llvm.lifetime.end.p0i8(i64 4, i8* %12) #4
-  %13 = bitcast i32* %var_six to i8*
+  %13 = bitcast i32* %var_eight to i8*
   call void @llvm.lifetime.end.p0i8(i64 4, i8* %13) #4
-  call void @llvm.lifetime.end.p0i8(i64 1, i8* %var_five) #4
-  %14 = bitcast i32* %var_four to i8*
+  %14 = bitcast i32* %var_seven to i8*
   call void @llvm.lifetime.end.p0i8(i64 4, i8* %14) #4
-  %15 = bitcast i32* %var_three to i8*
+  %15 = bitcast i32* %var_six to i8*
   call void @llvm.lifetime.end.p0i8(i64 4, i8* %15) #4
-  %16 = bitcast i32* %var_two to i8*
+  call void @llvm.lifetime.end.p0i8(i64 1, i8* %var_five) #4
+  %16 = bitcast i32* %var_four to i8*
   call void @llvm.lifetime.end.p0i8(i64 4, i8* %16) #4
-  %17 = bitcast i32* %var_one to i8*
+  %17 = bitcast i32* %var_three to i8*
   call void @llvm.lifetime.end.p0i8(i64 4, i8* %17) #4
+  %18 = bitcast i32* %var_two to i8*
+  call void @llvm.lifetime.end.p0i8(i64 4, i8* %18) #4
+  %19 = bitcast i32* %var_one to i8*
+  call void @llvm.lifetime.end.p0i8(i64 4, i8* %19) #4
   ret void
 }
 
@@ -174,8 +185,8 @@ define dso_local spir_func void @_Z3boov() #3 {
   %2 = bitcast %struct._ZTS7foo_two.foo_two* %1 to i8*
   call void @llvm.lifetime.start.p0i8(i64 44, i8* %2) #4
   %3 = bitcast %struct._ZTS7foo_two.foo_two* %1 to i8*
-  ; CHECK-LLVM: call void @llvm.var.annotation(i8* %[[VAR11:[a-zA-Z0-9_]+]], i8* getelementptr inbounds ([29 x i8], [29 x i8]* [[STR11]], i32 0, i32 0), i8* undef, i32 undef)
-  call void @llvm.var.annotation(i8* %3, i8* getelementptr inbounds ([29 x i8], [29 x i8]* @.str.11, i32 0, i32 0), i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str.1, i32 0, i32 0), i32 35)
+  ; CHECK-LLVM: call void @llvm.var.annotation(i8* %[[VAR12:[a-zA-Z0-9_]+]], i8* getelementptr inbounds ([29 x i8], [29 x i8]* [[STR12]], i32 0, i32 0), i8* undef, i32 undef)
+  call void @llvm.var.annotation(i8* %3, i8* getelementptr inbounds ([29 x i8], [29 x i8]* @.str.12, i32 0, i32 0), i8* getelementptr inbounds ([13 x i8], [13 x i8]* @.str.1, i32 0, i32 0), i32 35)
    %4 = bitcast %struct._ZTS7foo_two.foo_two* %1 to i8*
    call void @llvm.lifetime.end.p0i8(i64 44, i8* %4) #4
    ret void

diff --git a/test/IntelFPGAMemoryAttributesForStruct.ll b/test/IntelFPGAMemoryAttributesForStruct.ll
@@ -26,12 +26,14 @@
 ; CHECK-SPIRV: MemberDecorate {{[0-9]+}} 8 MaxReplicatesINTEL 4
 ; CHECK-SPIRV: MemberDecorate {{[0-9]+}} 9 SimpleDualPortINTEL
 ; CHECK-SPIRV: MemberDecorate {{[0-9]+}} 7 MergeINTEL "foobar" "width"
+; CHECK-SPIRV: MemberDecorate {{[0-9]+}} 0 BankBitsINTEL 42 41 40
 
 target datalayout = "e-i64:64-v16:16-v24:32-v32:32-v48:64-v96:128-v192:256-v256:256-v512:512-v1024:1024"
 target triple = "spir64-unknown-linux"
 
 %class.anon = type { i8 }
 %struct.foo = type { i32, i32, i32, i32, i8, i32, i32, i32, i32, i32 }
+%struct.s = type { i32 }
 
 %struct._ZTSZ20field_addrspace_castvE5state.state = type { [8 x i32] }
 
@@ -45,6 +47,7 @@ target triple = "spir64-unknown-linux"
 ; CHECK-LLVM: [[STR8:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{merge:foobar:width}
 ; CHECK-LLVM: [[STR9:@[0-9_.]+]] = {{.*}}{max_replicates:4}
 ; CHECK-LLVM: [[STR10:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{simple_dual_port:1}
+; CHECK-LLVM: [[STR12:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{numbanks:8}{bank_bits:42,41,40}
 ; CHECK-LLVM: [[STR11:@[0-9_.]+]] = {{.*}}{memory:DEFAULT}{numbanks:2}
 @.str = private unnamed_addr constant [29 x i8] c"{memory:DEFAULT}{numbanks:4}\00", section "llvm.metadata"
 @.str.1 = private unnamed_addr constant [16 x i8] c"test_struct.cpp\00", section "llvm.metadata"
@@ -58,6 +61,7 @@ target triple = "spir64-unknown-linux"
 @.str.9 = private unnamed_addr constant [19 x i8] c"{max_replicates:4}\00", section "llvm.metadata"
 @.str.10 = private unnamed_addr constant [37 x i8] c"{memory:DEFAULT}{simple_dual_port:1}\00", section "llvm.metadata"
 @.str.11 = private unnamed_addr constant [29 x i8] c"{memory:DEFAULT}{numbanks:2}\00", section "llvm.metadata"
+@.str.12 = private unnamed_addr constant [49 x i8] c"{memory:DEFAULT}{numbanks:8}{bank_bits:42,41,40}\00", section "llvm.metadata"
 
 ; Function Attrs: nounwind
 define spir_kernel void @_ZTSZ4mainE15kernel_function() #0 !kernel_arg_addr_space !4 !kernel_arg_access_qual !4 !kernel_arg_type !4 !kernel_arg_base_type !4 !kernel_arg_type_qual !4 {
@@ -81,6 +85,7 @@ entry:
   store %class.anon* %this, %class.anon** %this.addr, align 8, !tbaa !5
   %this1 = load %class.anon*, %class.anon** %this.addr, align 8
   call spir_func void @_Z3barv()
+  call spir_func void @_Z8bankbitsv()
   ret void
 }
 
@@ -148,6 +153,23 @@ entry:
   ret void
 }
 
+; Function Attrs: nounwind
+define spir_func void @_Z8bankbitsv() #3 {
+entry:
+  %s2 = alloca %struct.s, align 4
+  %0 = bitcast %struct.s* %s2 to i8*
+  call void @llvm.lifetime.start.p0i8(i64 4, i8* %0) #4
+  ; CHECK-LLVM: %[[FIELD:.*]] = getelementptr inbounds %struct.s, %struct.s* %{{[a-zA-Z0-9]+}}, i32 0, i32 0
+  ; CHECK-LLVM: %[[CAST:.*]] = bitcast{{.*}}%[[FIELD]]
+  ; CHECK-LLVM: call i8* @llvm.ptr.annotation.p0i8{{.*}}%[[CAST]]{{.*}}[[STR12]]
+  %a = getelementptr inbounds %struct.s, %struct.s* %s2, i32 0, i32 0
+  %1 = call i32* @llvm.ptr.annotation.p0i32(i32* %a, i8* getelementptr inbounds ([49 x i8], [49 x i8]* @.str.12, i32 0, i32 0), i8* getelementptr inbounds ([16 x i8], [16 x i8]* @.str.1, i32 0, i32 0), i32 84)
+  store i32 0, i32* %1, align 4, !tbaa !22
+  %2 = bitcast %struct.s* %s2 to i8*
+  call void @llvm.lifetime.end.p0i8(i64 4, i8* %2) #4
+  ret void
+}
+
 define spir_func void @_Z20field_addrspace_castv() #3 {
 entry:
   %state_var = alloca %struct._ZTSZ20field_addrspace_castvE5state.state, align 4
@@ -222,6 +244,9 @@ declare i32* @llvm.ptr.annotation.p0i32(i32*, i8*, i8*, i32) #4
 ; Function Attrs: nounwind
 declare i8 addrspace(4)* @llvm.ptr.annotation.p4i8(i8 addrspace(4)*, i8*, i8*, i32) #4
 
+; Function Attrs: nounwind
+declare i32* @llvm.ptr.annotation.p0i32(i32*, i8*, i8*, i32) #4
+
 attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "uniform-work-group-size"="true" "unsafe-fp-math"="false" "use-soft-float"="false" }
 attributes #1 = { argmemonly nounwind }
 attributes #2 = { inlinehint nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-frame-pointer-elim"="false" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" }
@@ -254,4 +279,6 @@ attributes #4 = { nounwind }
 !18 = !{!10, !11, i64 28}
 !19 = !{!10, !11, i64 32}
 !20 = !{!10, !11, i64 36}
-
+!21 = !{!10, !11, i64 40}
+!22 = !{!23, !11, i64 0}
+!23 = !{!"s", !11, i64 0}