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Hi @lorem-ipsum , thanks for contributing, A few comments I have during my review: For all devices:
Cheers, |
I'd prefer to keep the pin names as on the datasheet and not remove the "B" so the symbol and documentation match. KLC doesn't request this, either. GND pins can always be stacked. Power pins should be stacked unless there's a reason not to, like the datasheet requiring a decoupling cap on each pin. The top of page 22 of the datasheet and https://www.analog.com/media/en/technical-documentation/evaluation-documentation/53447263508842AD9513_14_15_RevB_Eval_Board_Schematic.pdf both indicate to me that each VS pin needs a cap, so yes, not stacking is the right way to go here. |
The datasheet indicate it is the complementary output, and we usually do that for example when a pin is "RSTn" or "CSn", they become "~RST" and "~CS". Joel |
KLC discusses overbars for logic low signals, and not complementary/differential signals. Here the usage of "B" in pin names is mixed. I would keep the "B" on outputs but it's uncommon (to me) for logic low inputs; for consistency maybe keep all "B"? IMO the overbar adds clarity and probably wouldn't cause any confusion so what you mention works me. This isn't really covered in KLC except for the part about the datasheet winning if there's conflict. What do you like? |
@evanshultz thanks to point me the difference, you're right it's not really some "logic low" in/out. |
@lorem-ipsum any news here ? Thanks for the update, Joel |
@lorem-ipsum no worries and thanks for the update of the symbol. Just notice one remaining issue:
Then only need to wait the LFCSP footprint before merging (KiCad/kicad-footprints#1426). Cheers, |
Good proposition of @evanshultz too ! |
That's great for me, just need to wait the footprint now. |
Footprint merged. Merging the symbols. |
This adds the clock distribution ICs AD9513, AD9514 and AD9515. They are very similar except their outputs. Footprint PR will follow. I placed VREF on top even though it is an output as there was space. It is used for the configuration of the S[0..10] pins. Alternatively I was thinking of splitting the part into two, moving the configuration to another part.