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Esp32 #722

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Misca1234
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Push ESP 32
https://www.espressif.com/sites/default/files/documentation/esp32_hardware_design_guidelines_en.pdf

It comes in two flavours, a 5x5 QFN and a 6x6 QFN

The symbol is exactly the same for both of them
ESP32-D0WDQ6 6x6
ESP32-D0WD, alias ESP32-D2WD, ESP32-S0WD 5x5

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Thanks for creating a pull request to contribute to the KiCad libraries! To speed up integration of your PR, please check the following items:

  • Provide a URL to a datasheet for the symbol(s) you are contributing
  • An example screenshot image is very helpful
  • Ensure that the associated footprints match the official footprint library
  • If there are matching footprint PRs, provide link(s) as appropriate
  • Check the output of the Travis automated check scripts - fix any errors as required

@antoniovazquezblanco antoniovazquezblanco added Pending reviewer A pull request waiting for a reviewer Addition Adds new symbols to library labels Oct 5, 2018
@poeschlr
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The datasheet you link is for a module not really for a qfn version. Is there a better datasheet available?

@Misca1234
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Misca1234 commented Dec 31, 2018

This one should be better, (the symbols have already this)
https://www.espressif.com/sites/default/files/documentation/esp32_datasheet_en.pdf

@myfreescalewebpage myfreescalewebpage self-assigned this Jan 17, 2019
@myfreescalewebpage myfreescalewebpage removed the Pending reviewer A pull request waiting for a reviewer label Jan 17, 2019
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myfreescalewebpage commented Jan 17, 2019

Hi @Misca1234 , thanks for contributing,

A few comments I have during my review:

ESP32-D0WD:

  • You can complete the description: Single 2.4 GHz Wi-Fi-and-Bluetooth combo chip, dual core, no internal flash, QFN-48 according to datasheet page 46
  • Footprint filter should be QFN*1EP*5x5mm*P0.35mm* (no EP size in it)
  • VDD* input pins should not be stacked
  • "VDD_SDIO" should be moved to the top of the symbol. Datasheet indicates a link with "VDD3P3_RTC", so I propose to get these two pins together on the right of the VDD* group
  • Name of pin 49 is "GND" only
  • I clearly do not understand how you have chosen to group the pins except for SD/Crystal/CAP/Sensor. Can you detail your logic ? Why MTCK not with MTDI etc for example.

ESP32-D0WDQ6:

  • Footprint filter should be QFN*1EP*6x6mm*P0.4mm*
  • VDD* input pins should not be stacked
  • "VDD_SDIO" should be moved to the top of the symbol. Datasheet indicates a link with "VDD3P3_RTC", so I propose to get these two pins together on the right of the VDD* group
  • Name of pin 49 is "GND" only
  • I clearly do not understand how you have chosen to group the pins except for SD/Crystal/CAP/Sensor. Can you detail your logic ? Why MTCK not with MTDI etc for example.

ESP8089:

  • Datasheet link is broken, I have found only "http://gamma.spb.ru/images/pdf/esp8089_datasheet_en.pdf", have you got a better one ?
  • Footprint should be Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.7x3.7mm according to datasheet page 18
  • Footprint filter should be QFN*1EP*5x5mm*P0.5mm*
  • VDD* input pins should not be stacked
  • Name of pin 7 is ~CHIP_PU
  • Pin 24 id "GPIO5", it is not a Power supply pin
  • Name of pin 32 should be ~EXT_RST to get the over-bar (B indicate active low)
  • Name of pin 33 is "GND" only
  • Type of pin "RES12K" should be Passive to avoid ERC errors
  • Type of pin 29 "VDDD" is Power Input

Cheers,
Joel

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Misca1234 commented Jan 20, 2019

ESP32-D0WD:

You can complete the description: Single 2.4 GHz Wi-Fi-and-Bluetooth combo chip, dual core, no internal flash, QFN-48 according to datasheet page 46

Changed

Footprint filter should be QFN1EP5x5mmP0.35mm (no EP size in it)

Changed

VDD* input pins should not be stacked

They are seperated

"VDD_SDIO" should be moved to the top of the symbol.

It is placed as in accordance to a normal power regulator output

Name of pin 49 is "GND" only

Changed

I clearly do not understand how you have chosen to group the pins
MTDI, GPIO0, GPIO2, MTDO, GPIO5
is grouped as strapped pins, page 11,
there are other ways to group, such as JTAG etc.

SD_CMD, SD_CLK, SD_DATA_0, SD_DATA_1, SD_DATA_2
Is grouped for SPI, page 30

MTCK, MTMS, there was room for them there

ESP32-D0WDQ6:

Footprint filter should be QFN1EP6x6mmP0.4mm

Changed

VDD* input pins should not be stacked

Changed

"VDD_SDIO" should be moved to the top of the symbol.

It is placed as in accordance to a normal power regulator output

Name of pin 49 is "GND" only

Changed

I clearly do not understand how you

As before

ESP8089:

Datasheet link is broken

We can try this one
https://www.espressif.com/sites/default/files/documentation/0a-esp8285_datasheet_en.pdf

Footprint should be Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.7x3.7mm according to datasheet page 18

This does not exist, keeping current one or we should add the 3.7x3.7

Footprint filter should be QFN1EP5x5mmP0.5mm

Changed

VDD* input pins should not be stacked

Changed

Name of pin 7 is ~CHIP_PU

We are not reading same data sheet, mine says this

bild

Pin 24 id "GPIO5", it is not a Power supply pin

Changed

Name of pin 32 should be ~EXT_RST to get the over-bar (B indicate active low)

Tilde added to beginning of string to indicate active low

Name of pin 33 is "GND" only

Changed

Type of pin "RES12K" should be Passive to avoid ERC errors

It is an input according to the data sheet, If there is a bug in
ERF checker then ERC checker should be fixed instead

Type of pin 29 "VDDD" is Power Input

Changed

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Hello @Misca1234

VDD* input pins should not be stacked
They are seperated

They are not all separated today, you should.

"VDD_SDIO" should be moved to the top of the symbol.
It is placed as in accordance to a normal power regulator output

Regulator output on the right is an accepted KLC exception. Other MCU have "VDD CORE" power output, always placed on the top. So this one should complies with the KLC too.

Datasheet link is broken
We can try this one
https://www.espressif.com/sites/default/files/documentation/0a-esp8285_datasheet_en.pdf

I don't think it applies to ESP8089. It is ESP8285 only.

Footprint should be Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.7x3.7mm according to datasheet page 18
This does not exist, keeping current one or we should add the 3.7x3.7

You should create it with the scripts and make a PR, it is not allowed to round this.

Name of pin 7 is ~CHIP_PU
We are not reading same data sheet, mine says this

I will be happy to remove my comment if you provide the right datasheet :)

Name of pin 32 should be ~EXT_RST to get the over-bar (B indicate active low)
Tilde added to beginning of string to indicate active low

You should also remove the "B"

Type of pin "RES12K" should be Passive to avoid ERC errors
It is an input according to the data sheet, If there is a bug in
ERF checker then ERC checker should be fixed instead

The ERC check has limitations and it is not possible to handle every thing. We use Passive for this kind of pins in several hundred of devices (and maybe more!).

Joel

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@Misca1234 any news here ? Thanks !

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Misca1234 commented Mar 10, 2019

any news here

No, not really

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No news from the original author, indicate it is abandoned.

@myfreescalewebpage myfreescalewebpage added the Abandoned Original author has stopped working on the PR label Jul 29, 2019
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