Syncing from original

Notes

@@ -0,0 +1 @@
+Probably fails due to lack of comparator core (maybe this is generated by Spectrum or Oscillo instruments) - it should be generated in the tmp folder.

boards/snickerdoodle/PART

@@ -0,0 +1 @@
+xc7z010clg400-1

boards/snickerdoodle/config/board_preset.tcl

@@ -0,0 +1,50 @@
+set_property -dict [ list \
+CONFIG.PCW_APU_PERIPHERAL_FREQMHZ {666.666666} \
+CONFIG.PCW_ENET0_PERIPHERAL_ENABLE {0} \
+CONFIG.PCW_GPIO_EMIO_GPIO_ENABLE {1} \
+CONFIG.PCW_GPIO_MIO_GPIO_ENABLE {1} \
+CONFIG.PCW_GPIO_MIO_GPIO_IO {MIO} \
+CONFIG.PCW_IRQ_F2P_INTR {1} \
+CONFIG.PCW_PRESET_BANK0_VOLTAGE {LVCMOS 1.8V} \
+CONFIG.PCW_PRESET_BANK1_VOLTAGE {LVCMOS 1.8V} \
+CONFIG.PCW_QSPI_GRP_SINGLE_SS_ENABLE {1} \
+CONFIG.PCW_QSPI_PERIPHERAL_ENABLE {1} \
+CONFIG.PCW_QSPI_QSPI_IO {MIO 1 .. 6} \
+CONFIG.PCW_SD0_PERIPHERAL_ENABLE {1} \
+CONFIG.PCW_SD0_SD0_IO {MIO 40 .. 45} \
+CONFIG.PCW_SD1_PERIPHERAL_ENABLE {1} \
+CONFIG.PCW_SD1_SD1_IO {MIO 10 .. 15} \
+CONFIG.PCW_SPI1_PERIPHERAL_ENABLE {1} \
+CONFIG.PCW_SPI1_SPI1_IO {MIO 46 .. 51} \
+CONFIG.PCW_TRACE_PERIPHERAL_ENABLE {0} \
+CONFIG.PCW_UART0_PERIPHERAL_ENABLE {1} \
+CONFIG.PCW_UART0_UART0_IO {MIO 50 .. 51} \
+CONFIG.PCW_UART1_PERIPHERAL_ENABLE {0} \
+CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY0 {0.436} \
+CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY1 {0.436} \
+CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY2 {0.436} \
+CONFIG.PCW_UIPARAM_DDR_BOARD_DELAY3 {0.436} \
+CONFIG.PCW_UIPARAM_DDR_CL {6} \
+CONFIG.PCW_UIPARAM_DDR_COL_ADDR_COUNT {11} \
+CONFIG.PCW_UIPARAM_DDR_DEVICE_CAPACITY {8192 MBits} \
+CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_0 {0.004} \
+CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_1 {0.004} \
+CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_2 {0.004} \
+CONFIG.PCW_UIPARAM_DDR_DQS_TO_CLK_DELAY_3 {0.004} \
+CONFIG.PCW_UIPARAM_DDR_DRAM_WIDTH {32 Bits} \
+CONFIG.PCW_UIPARAM_DDR_MEMORY_TYPE {LPDDR 2} \
+CONFIG.PCW_UIPARAM_DDR_PARTNO {Custom} \
+CONFIG.PCW_UIPARAM_DDR_ROW_ADDR_COUNT {14} \
+CONFIG.PCW_UIPARAM_DDR_SPEED_BIN {LPDDR2_1066} \
+CONFIG.PCW_UIPARAM_DDR_T_FAW {50.0} \
+CONFIG.PCW_UIPARAM_DDR_T_RAS_MIN {42.0} \
+CONFIG.PCW_UIPARAM_DDR_T_RC {63.0} \
+CONFIG.PCW_UIPARAM_DDR_T_RCD {8} \
+CONFIG.PCW_UIPARAM_DDR_T_RP {9} \
+CONFIG.PCW_UIPARAM_GENERATE_SUMMARY {NONE} \
+CONFIG.PCW_USB0_PERIPHERAL_ENABLE {0} \
+CONFIG.PCW_USE_FABRIC_INTERRUPT {0} \
+CONFIG.PCW_USE_M_AXI_GP1 {0} \
+] [get_bd_cells ${::ps_name}]
+
+