Fixed allowlist header comments to use double ##

LLNL · Sep 20, 2023 · d1daa77 · d1daa77
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diff --git a/allowlists/al_06_2A b/allowlists/al_06_2A
@@ -1,12 +1,12 @@
-# This file contains the model-specific registers available in 06_2A processors
-# based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
-# Software Development Manual (335592-079US March 2023).
-# Uncommenting allows reading a particular MSR.
-# Modifying the write mask allows writing to those particular bits.
-# Be sure to cat the modified list into /dev/cpu/msr_allowlist.
-# See the README file for more details.
-#
-# MSR        # Write Mask       # Comment
+## This file contains the model-specific registers available in 06_2A processors
+## based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
+## Software Development Manual (335592-079US March 2023).
+## Uncommenting allows reading a particular MSR.
+## Modifying the write mask allows writing to those particular bits.
+## Be sure to cat the modified list into /dev/cpu/msr_allowlist.
+## See the README file for more details.
+##
+## MSR        # Write Mask       # Comment
 # 0x00000000 0x0000000000000000 # "IA32_P5_MC_ADDR (Table: 2-20)"
 # 0x00000001 0x0000000000000000 # "IA32_P5_MC_TYPE (Table: 2-20)"
 # 0x00000006 0x0000000000000000 # "IA32_MONITOR_FILTER_SIZE (Table: 2-20)"

diff --git a/allowlists/al_06_2D b/allowlists/al_06_2D
@@ -1,12 +1,12 @@
-# This file contains the model-specific registers available in 06_2D processors
-# based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
-# Software Development Manual (335592-079US March 2023).
-# Uncommenting allows reading a particular MSR.
-# Modifying the write mask allows writing to those particular bits.
-# Be sure to cat the modified list into /dev/cpu/msr_allowlist.
-# See the README file for more details.
-#
-# MSR        # Write Mask       # Comment
+## This file contains the model-specific registers available in 06_2D processors
+## based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
+## Software Development Manual (335592-079US March 2023).
+## Uncommenting allows reading a particular MSR.
+## Modifying the write mask allows writing to those particular bits.
+## Be sure to cat the modified list into /dev/cpu/msr_allowlist.
+## See the README file for more details.
+##
+## MSR        # Write Mask       # Comment
 # 0x00000000 0x0000000000000000 # "IA32_P5_MC_ADDR (Table: 2-20)"
 # 0x00000001 0x0000000000000000 # "IA32_P5_MC_TYPE (Table: 2-20)"
 # 0x00000006 0x0000000000000000 # "IA32_MONITOR_FILTER_SIZE (Table: 2-20)"

diff --git a/allowlists/al_06_3A b/allowlists/al_06_3A
@@ -1,12 +1,12 @@
-# This file contains the model-specific registers available in 06_3A processors
-# based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
-# Software Development Manual (335592-079US March 2023).
-# Uncommenting allows reading a particular MSR.
-# Modifying the write mask allows writing to those particular bits.
-# Be sure to cat the modified list into /dev/cpu/msr_allowlist.
-# See the README file for more details.
-#
-# MSR        # Write Mask       # Comment
+## This file contains the model-specific registers available in 06_3A processors
+## based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
+## Software Development Manual (335592-079US March 2023).
+## Uncommenting allows reading a particular MSR.
+## Modifying the write mask allows writing to those particular bits.
+## Be sure to cat the modified list into /dev/cpu/msr_allowlist.
+## See the README file for more details.
+##
+## MSR        # Write Mask       # Comment
 # 0x00000000 0x0000000000000000 # "IA32_P5_MC_ADDR (Table: 2-20)"
 # 0x00000001 0x0000000000000000 # "IA32_P5_MC_TYPE (Table: 2-20)"
 # 0x00000006 0x0000000000000000 # "IA32_MONITOR_FILTER_SIZE (Table: 2-20)"

diff --git a/allowlists/al_06_3C b/allowlists/al_06_3C
@@ -1,12 +1,12 @@
-# This file contains the model-specific registers available in 06_3C processors
-# based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
-# Software Development Manual (335592-079US March 2023).
-# Uncommenting allows reading a particular MSR.
-# Modifying the write mask allows writing to those particular bits.
-# Be sure to cat the modified list into /dev/cpu/msr_allowlist.
-# See the README file for more details.
-#
-# MSR        # Write Mask       # Comment
+## This file contains the model-specific registers available in 06_3C processors
+## based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
+## Software Development Manual (335592-079US March 2023).
+## Uncommenting allows reading a particular MSR.
+## Modifying the write mask allows writing to those particular bits.
+## Be sure to cat the modified list into /dev/cpu/msr_allowlist.
+## See the README file for more details.
+##
+## MSR        # Write Mask       # Comment
 # 0x00000000 0x0000000000000000 # "IA32_P5_MC_ADDR (Table: 2-20)"
 # 0x00000001 0x0000000000000000 # "IA32_P5_MC_TYPE (Table: 2-20)"
 # 0x00000006 0x0000000000000000 # "IA32_MONITOR_FILTER_SIZE (Table: 2-20)"

diff --git a/allowlists/al_06_3D b/allowlists/al_06_3D
@@ -1,12 +1,12 @@
-# This file contains the model-specific registers available in 06_3D processors
-# based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
-# Software Development Manual (335592-079US March 2023).
-# Uncommenting allows reading a particular MSR.
-# Modifying the write mask allows writing to those particular bits.
-# Be sure to cat the modified list into /dev/cpu/msr_allowlist.
-# See the README file for more details.
-#
-# MSR        # Write Mask       # Comment
+## This file contains the model-specific registers available in 06_3D processors
+## based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
+## Software Development Manual (335592-079US March 2023).
+## Uncommenting allows reading a particular MSR.
+## Modifying the write mask allows writing to those particular bits.
+## Be sure to cat the modified list into /dev/cpu/msr_allowlist.
+## See the README file for more details.
+##
+## MSR        # Write Mask       # Comment
 # 0x00000000 0x0000000000000000 # "IA32_P5_MC_ADDR (Table: 2-20)"
 # 0x00000001 0x0000000000000000 # "IA32_P5_MC_TYPE (Table: 2-20)"
 # 0x00000006 0x0000000000000000 # "IA32_MONITOR_FILTER_SIZE (Table: 2-20)"

diff --git a/allowlists/al_06_3E b/allowlists/al_06_3E
@@ -1,12 +1,12 @@
-# This file contains the model-specific registers available in 06_3E processors
-# based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
-# Software Development Manual (335592-079US March 2023).
-# Uncommenting allows reading a particular MSR.
-# Modifying the write mask allows writing to those particular bits.
-# Be sure to cat the modified list into /dev/cpu/msr_allowlist.
-# See the README file for more details.
-#
-# MSR        # Write Mask       # Comment
+## This file contains the model-specific registers available in 06_3E processors
+## based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
+## Software Development Manual (335592-079US March 2023).
+## Uncommenting allows reading a particular MSR.
+## Modifying the write mask allows writing to those particular bits.
+## Be sure to cat the modified list into /dev/cpu/msr_allowlist.
+## See the README file for more details.
+##
+## MSR        # Write Mask       # Comment
 # 0x00000000 0x0000000000000000 # "IA32_P5_MC_ADDR (Table: 2-20)"
 # 0x00000001 0x0000000000000000 # "IA32_P5_MC_TYPE (Table: 2-20)"
 # 0x00000006 0x0000000000000000 # "IA32_MONITOR_FILTER_SIZE (Table: 2-20)"

diff --git a/allowlists/al_06_3F b/allowlists/al_06_3F
@@ -1,12 +1,12 @@
-# This file contains the model-specific registers available in 06_3F processors
-# based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
-# Software Development Manual (335592-079US March 2023).
-# Uncommenting allows reading a particular MSR.
-# Modifying the write mask allows writing to those particular bits.
-# Be sure to cat the modified list into /dev/cpu/msr_allowlist.
-# See the README file for more details.
-#
-# MSR        # Write Mask       # Comment
+## This file contains the model-specific registers available in 06_3F processors
+## based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
+## Software Development Manual (335592-079US March 2023).
+## Uncommenting allows reading a particular MSR.
+## Modifying the write mask allows writing to those particular bits.
+## Be sure to cat the modified list into /dev/cpu/msr_allowlist.
+## See the README file for more details.
+##
+## MSR        # Write Mask       # Comment
 # 0x00000000 0x0000000000000000 # "IA32_P5_MC_ADDR (Table: 2-20)"
 # 0x00000001 0x0000000000000000 # "IA32_P5_MC_TYPE (Table: 2-20)"
 # 0x00000006 0x0000000000000000 # "IA32_MONITOR_FILTER_SIZE (Table: 2-20)"

diff --git a/allowlists/al_06_45 b/allowlists/al_06_45
@@ -1,12 +1,12 @@
-# This file contains the model-specific registers available in 06_45 processors
-# based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
-# Software Development Manual (335592-079US March 2023).
-# Uncommenting allows reading a particular MSR.
-# Modifying the write mask allows writing to those particular bits.
-# Be sure to cat the modified list into /dev/cpu/msr_allowlist.
-# See the README file for more details.
-#
-# MSR        # Write Mask       # Comment
+## This file contains the model-specific registers available in 06_45 processors
+## based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
+## Software Development Manual (335592-079US March 2023).
+## Uncommenting allows reading a particular MSR.
+## Modifying the write mask allows writing to those particular bits.
+## Be sure to cat the modified list into /dev/cpu/msr_allowlist.
+## See the README file for more details.
+##
+## MSR        # Write Mask       # Comment
 # 0x00000000 0x0000000000000000 # "IA32_P5_MC_ADDR (Table: 2-20)"
 # 0x00000001 0x0000000000000000 # "IA32_P5_MC_TYPE (Table: 2-20)"
 # 0x00000006 0x0000000000000000 # "IA32_MONITOR_FILTER_SIZE (Table: 2-20)"

diff --git a/allowlists/al_06_46 b/allowlists/al_06_46
@@ -1,12 +1,12 @@
-# This file contains the model-specific registers available in 06_46 processors
-# based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
-# Software Development Manual (335592-079US March 2023).
-# Uncommenting allows reading a particular MSR.
-# Modifying the write mask allows writing to those particular bits.
-# Be sure to cat the modified list into /dev/cpu/msr_allowlist.
-# See the README file for more details.
-#
-# MSR        # Write Mask       # Comment
+## This file contains the model-specific registers available in 06_46 processors
+## based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
+## Software Development Manual (335592-079US March 2023).
+## Uncommenting allows reading a particular MSR.
+## Modifying the write mask allows writing to those particular bits.
+## Be sure to cat the modified list into /dev/cpu/msr_allowlist.
+## See the README file for more details.
+##
+## MSR        # Write Mask       # Comment
 # 0x00000000 0x0000000000000000 # "IA32_P5_MC_ADDR (Table: 2-20)"
 # 0x00000001 0x0000000000000000 # "IA32_P5_MC_TYPE (Table: 2-20)"
 # 0x00000006 0x0000000000000000 # "IA32_MONITOR_FILTER_SIZE (Table: 2-20)"

diff --git a/allowlists/al_06_47 b/allowlists/al_06_47
@@ -1,12 +1,12 @@
-# This file contains the model-specific registers available in 06_47 processors
-# based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
-# Software Development Manual (335592-079US March 2023).
-# Uncommenting allows reading a particular MSR.
-# Modifying the write mask allows writing to those particular bits.
-# Be sure to cat the modified list into /dev/cpu/msr_allowlist.
-# See the README file for more details.
-#
-# MSR        # Write Mask       # Comment
+## This file contains the model-specific registers available in 06_47 processors
+## based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
+## Software Development Manual (335592-079US March 2023).
+## Uncommenting allows reading a particular MSR.
+## Modifying the write mask allows writing to those particular bits.
+## Be sure to cat the modified list into /dev/cpu/msr_allowlist.
+## See the README file for more details.
+##
+## MSR        # Write Mask       # Comment
 # 0x00000000 0x0000000000000000 # "IA32_P5_MC_ADDR (Table: 2-20)"
 # 0x00000001 0x0000000000000000 # "IA32_P5_MC_TYPE (Table: 2-20)"
 # 0x00000006 0x0000000000000000 # "IA32_MONITOR_FILTER_SIZE (Table: 2-20)"

diff --git a/allowlists/al_06_4E b/allowlists/al_06_4E
@@ -1,12 +1,12 @@
-# This file contains the model-specific registers available in 06_4E processors
-# based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
-# Software Development Manual (335592-079US March 2023).
-# Uncommenting allows reading a particular MSR.
-# Modifying the write mask allows writing to those particular bits.
-# Be sure to cat the modified list into /dev/cpu/msr_allowlist.
-# See the README file for more details.
-#
-# MSR        # Write Mask       # Comment
+## This file contains the model-specific registers available in 06_4E processors
+## based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
+## Software Development Manual (335592-079US March 2023).
+## Uncommenting allows reading a particular MSR.
+## Modifying the write mask allows writing to those particular bits.
+## Be sure to cat the modified list into /dev/cpu/msr_allowlist.
+## See the README file for more details.
+##
+## MSR        # Write Mask       # Comment
 # 0x00000000 0x0000000000000000 # "IA32_P5_MC_ADDR (Table: 2-20)"
 # 0x00000001 0x0000000000000000 # "IA32_P5_MC_TYPE (Table: 2-20)"
 # 0x00000006 0x0000000000000000 # "IA32_MONITOR_FILTER_SIZE (Table: 2-20)"

diff --git a/allowlists/al_06_4F b/allowlists/al_06_4F
@@ -1,12 +1,12 @@
-# This file contains the model-specific registers available in 06_4F processors
-# based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
-# Software Development Manual (335592-079US March 2023).
-# Uncommenting allows reading a particular MSR.
-# Modifying the write mask allows writing to those particular bits.
-# Be sure to cat the modified list into /dev/cpu/msr_allowlist.
-# See the README file for more details.
-#
-# MSR        # Write Mask       # Comment
+## This file contains the model-specific registers available in 06_4F processors
+## based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
+## Software Development Manual (335592-079US March 2023).
+## Uncommenting allows reading a particular MSR.
+## Modifying the write mask allows writing to those particular bits.
+## Be sure to cat the modified list into /dev/cpu/msr_allowlist.
+## See the README file for more details.
+##
+## MSR        # Write Mask       # Comment
 # 0x00000000 0x0000000000000000 # "IA32_P5_MC_ADDR (Table: 2-20)"
 # 0x00000001 0x0000000000000000 # "IA32_P5_MC_TYPE (Table: 2-20)"
 # 0x00000006 0x0000000000000000 # "IA32_MONITOR_FILTER_SIZE (Table: 2-20)"

diff --git a/allowlists/al_06_55 b/allowlists/al_06_55
@@ -1,12 +1,12 @@
-# This file contains the model-specific registers available in 06_55 processors
-# based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
-# Software Development Manual (335592-079US March 2023).
-# Uncommenting allows reading a particular MSR.
-# Modifying the write mask allows writing to those particular bits.
-# Be sure to cat the modified list into /dev/cpu/msr_allowlist.
-# See the README file for more details.
-#
-# MSR        # Write Mask       # Comment
+## This file contains the model-specific registers available in 06_55 processors
+## based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
+## Software Development Manual (335592-079US March 2023).
+## Uncommenting allows reading a particular MSR.
+## Modifying the write mask allows writing to those particular bits.
+## Be sure to cat the modified list into /dev/cpu/msr_allowlist.
+## See the README file for more details.
+##
+## MSR        # Write Mask       # Comment
 # 0x00000000 0x0000000000000000 # "IA32_P5_MC_ADDR (Table: 2-20)"
 # 0x00000001 0x0000000000000000 # "IA32_P5_MC_TYPE (Table: 2-20)"
 # 0x00000006 0x0000000000000000 # "IA32_MONITOR_FILTER_SIZE (Table: 2-20)"

diff --git a/allowlists/al_06_56 b/allowlists/al_06_56
@@ -1,12 +1,12 @@
-# This file contains the model-specific registers available in 06_56 processors
-# based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
-# Software Development Manual (335592-079US March 2023).
-# Uncommenting allows reading a particular MSR.
-# Modifying the write mask allows writing to those particular bits.
-# Be sure to cat the modified list into /dev/cpu/msr_allowlist.
-# See the README file for more details.
-#
-# MSR        # Write Mask       # Comment
+## This file contains the model-specific registers available in 06_56 processors
+## based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
+## Software Development Manual (335592-079US March 2023).
+## Uncommenting allows reading a particular MSR.
+## Modifying the write mask allows writing to those particular bits.
+## Be sure to cat the modified list into /dev/cpu/msr_allowlist.
+## See the README file for more details.
+##
+## MSR        # Write Mask       # Comment
 # 0x00000000 0x0000000000000000 # "IA32_P5_MC_ADDR (Table: 2-20)"
 # 0x00000001 0x0000000000000000 # "IA32_P5_MC_TYPE (Table: 2-20)"
 # 0x00000006 0x0000000000000000 # "IA32_MONITOR_FILTER_SIZE (Table: 2-20)"

diff --git a/allowlists/al_06_5E b/allowlists/al_06_5E
@@ -1,12 +1,12 @@
-# This file contains the model-specific registers available in 06_5E processors
-# based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
-# Software Development Manual (335592-079US March 2023).
-# Uncommenting allows reading a particular MSR.
-# Modifying the write mask allows writing to those particular bits.
-# Be sure to cat the modified list into /dev/cpu/msr_allowlist.
-# See the README file for more details.
-#
-# MSR        # Write Mask       # Comment
+## This file contains the model-specific registers available in 06_5E processors
+## based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
+## Software Development Manual (335592-079US March 2023).
+## Uncommenting allows reading a particular MSR.
+## Modifying the write mask allows writing to those particular bits.
+## Be sure to cat the modified list into /dev/cpu/msr_allowlist.
+## See the README file for more details.
+##
+## MSR        # Write Mask       # Comment
 # 0x00000000 0x0000000000000000 # "IA32_P5_MC_ADDR (Table: 2-20)"
 # 0x00000001 0x0000000000000000 # "IA32_P5_MC_TYPE (Table: 2-20)"
 # 0x00000006 0x0000000000000000 # "IA32_MONITOR_FILTER_SIZE (Table: 2-20)"

diff --git a/allowlists/al_06_66 b/allowlists/al_06_66
@@ -1,12 +1,12 @@
-# This file contains the model-specific registers available in 06_66 processors
-# based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
-# Software Development Manual (335592-079US March 2023).
-# Uncommenting allows reading a particular MSR.
-# Modifying the write mask allows writing to those particular bits.
-# Be sure to cat the modified list into /dev/cpu/msr_allowlist.
-# See the README file for more details.
-#
-# MSR        # Write Mask       # Comment
+## This file contains the model-specific registers available in 06_66 processors
+## based on a close reading of volume 4 of the Intel 64 and IA-32 Architectures
+## Software Development Manual (335592-079US March 2023).
+## Uncommenting allows reading a particular MSR.
+## Modifying the write mask allows writing to those particular bits.
+## Be sure to cat the modified list into /dev/cpu/msr_allowlist.
+## See the README file for more details.
+##
+## MSR        # Write Mask       # Comment
 # 0x00000000 0x0000000000000000 # "IA32_P5_MC_ADDR (Table: 2-20)"
 # 0x00000001 0x0000000000000000 # "IA32_P5_MC_TYPE (Table: 2-20)"
 # 0x00000006 0x0000000000000000 # "IA32_MONITOR_FILTER_SIZE (Table: 2-20)"