ECE3700J Introduction to Computer Organization (Fall 2023) Lab Repository

Author

• Kezhi Li little_black@sjtu.edu.cn
• Xuqing Yang catalpa-bungei@sjtu.edu.cn
• Zeqing Wang der-zing@sjtu.edu.cn

Brief Introduction

This repository is for the lab of ECE3700J Introduction to Computer Organization (Fall 2023) in UM-SJTU JI. The lab is divided into 3 parts, and each part has its own folder. The details of each part are as follows:

• Pipelineprocessor: A 5-stage pipeline processor with forwarding and hazard detection.
• Cache: A cache with no associative design policy.
• TLB: Contains a TLB and a page table interacting with cache and main memory.

How to use

iverilog -o <output> <input>
vvp <output>

About Honor Code

• If there are similar questions or labs in the future, it is the responsibility of JI students not to copy or modify these codes because it is against the Honor Code.
• The owner of this repository should not take any commitment for other's faults.