This is the final project for the course "Advances in System-on-Chip Design" taught by of Prof. Pilato to PhD students at Politecnico di Milano (Italy). The final project presentation is available here.
The project was done in collaboration with Simone Salgaro.
This project enables accesses to separate memory spaces into gem5.
Emerging mixed-volatile platforms, such as the MSP430-FRxxxx from Texas Instruments, feature an internal Non Volatile Memory (NVM) that is directly addressable from the MCU. Such platforms allow programs to directly access either volatile or non-volatile memory, while considering the two memories as two separate memory spaces. At the time of the project, the NVM support of gem5 does not allow such behavior, as the entire memory is considered as a single memory space.
This project aims at enabling direct accesses to separate memory spaces, so that we can simulate the behavior of emerging mixed-volatility platforms.
The gem5-20.1 folder contains the patched version of gem5 that supports separate memory spaces.
We provide a guide that shows how to simulate a NVM into gem5, and how to patch and use gem5 20.1 for accessing separate memory spaces here.
Finally, we show a practical example with a multi-core system that uses a Network-on-Chip here.
A docker image for compiling gem5 is available in the docker folder.
The benchmarks were taken from the MiBench2 benchmarking suite.