Add support for Tronxy V10 with TFT_TRONXY_X5SA and MKS_ROBIN_TFT43 screens

Marlin/src/HAL/STM32/tft/tft_fsmc.cpp

@@ -37,50 +37,61 @@ LCD_CONTROLLER_TypeDef *TFT_FSMC::LCD;
 
 void TFT_FSMC::init() {
   uint32_t controllerAddress;
-  FSMC_NORSRAM_TimingTypeDef timing, extTiming;
+  FMC_OR_FSMC(NORSRAM_TimingTypeDef) timing, extTiming;
 
   uint32_t nsBank = (uint32_t)pinmap_peripheral(digitalPinToPinName(TFT_CS_PIN), pinMap_FSMC_CS);
 
   // Perform the SRAM1 memory initialization sequence
-  SRAMx.Instance = FSMC_NORSRAM_DEVICE;
-  SRAMx.Extended = FSMC_NORSRAM_EXTENDED_DEVICE;
+  SRAMx.Instance = FMC_OR_FSMC(NORSRAM_DEVICE);
+  SRAMx.Extended = FMC_OR_FSMC(NORSRAM_EXTENDED_DEVICE);
+
   // SRAMx.Init
   SRAMx.Init.NSBank = nsBank;
-  SRAMx.Init.DataAddressMux = FSMC_DATA_ADDRESS_MUX_DISABLE;
-  SRAMx.Init.MemoryType = FSMC_MEMORY_TYPE_SRAM;
-  SRAMx.Init.MemoryDataWidth = TERN(TFT_INTERFACE_FSMC_8BIT, FSMC_NORSRAM_MEM_BUS_WIDTH_8, FSMC_NORSRAM_MEM_BUS_WIDTH_16);
-  SRAMx.Init.BurstAccessMode = FSMC_BURST_ACCESS_MODE_DISABLE;
-  SRAMx.Init.WaitSignalPolarity = FSMC_WAIT_SIGNAL_POLARITY_LOW;
-  SRAMx.Init.WrapMode = FSMC_WRAP_MODE_DISABLE;
-  SRAMx.Init.WaitSignalActive = FSMC_WAIT_TIMING_BEFORE_WS;
-  SRAMx.Init.WriteOperation = FSMC_WRITE_OPERATION_ENABLE;
-  SRAMx.Init.WaitSignal = FSMC_WAIT_SIGNAL_DISABLE;
-  SRAMx.Init.ExtendedMode = FSMC_EXTENDED_MODE_ENABLE;
-  SRAMx.Init.AsynchronousWait = FSMC_ASYNCHRONOUS_WAIT_DISABLE;
-  SRAMx.Init.WriteBurst = FSMC_WRITE_BURST_DISABLE;
-  #ifdef STM32F4xx
-    SRAMx.Init.PageSize = FSMC_PAGE_SIZE_NONE;
+  SRAMx.Init.DataAddressMux     = FMC_OR_FSMC(DATA_ADDRESS_MUX_DISABLE);
+  SRAMx.Init.MemoryType         = FMC_OR_FSMC(MEMORY_TYPE_SRAM);
+  #ifdef STM32F446xx
+    SRAMx.Init.MemoryDataWidth  = TERN(TFT_INTERFACE_FMC_8BIT, FMC_NORSRAM_MEM_BUS_WIDTH_8, FMC_NORSRAM_MEM_BUS_WIDTH_16);
+  #else
+    SRAMx.Init.MemoryDataWidth  = TERN(TFT_INTERFACE_FSMC_8BIT, FSMC_NORSRAM_MEM_BUS_WIDTH_8, FSMC_NORSRAM_MEM_BUS_WIDTH_16);
+  #endif
+  SRAMx.Init.BurstAccessMode    = FMC_OR_FSMC(BURST_ACCESS_MODE_DISABLE);
+  SRAMx.Init.WaitSignalPolarity = FMC_OR_FSMC(WAIT_SIGNAL_POLARITY_LOW);
+  SRAMx.Init.WrapMode           = FMC_OR_FSMC(WRAP_MODE_DISABLE);
+  SRAMx.Init.WaitSignalActive   = FMC_OR_FSMC(WAIT_TIMING_BEFORE_WS);
+  SRAMx.Init.WriteOperation     = FMC_OR_FSMC(WRITE_OPERATION_ENABLE);
+  SRAMx.Init.WaitSignal         = FMC_OR_FSMC(WAIT_SIGNAL_DISABLE);
+  SRAMx.Init.ExtendedMode       = FMC_OR_FSMC(EXTENDED_MODE_ENABLE);
+  SRAMx.Init.AsynchronousWait   = FMC_OR_FSMC(ASYNCHRONOUS_WAIT_DISABLE);
+  SRAMx.Init.WriteBurst         = FMC_OR_FSMC(WRITE_BURST_DISABLE);
+  #if defined(STM32F446xx) || defined(STM32F4xx)
+    SRAMx.Init.PageSize         = FMC_OR_FSMC(PAGE_SIZE_NONE);
   #endif
+
   // Read Timing - relatively slow to ensure ID information is correctly read from TFT controller
-  // Can be decreases from 15-15-24 to 4-4-8 with risk of stability loss
-  timing.AddressSetupTime = 15;
-  timing.AddressHoldTime = 15;
-  timing.DataSetupTime = 24;
-  timing.BusTurnAroundDuration = 0;
-  timing.CLKDivision = 16;
-  timing.DataLatency = 17;
-  timing.AccessMode = FSMC_ACCESS_MODE_A;
+  // Can be decreased from 15-15-24 to 4-4-8 with risk of stability loss
+  timing.AddressSetupTime         = 15;
+  timing.AddressHoldTime          = 15;
+  timing.DataSetupTime            = 24;
+  timing.BusTurnAroundDuration    =  0;
+  timing.CLKDivision              = 16;
+  timing.DataLatency              = 17;
+  timing.AccessMode               = FMC_OR_FSMC(ACCESS_MODE_A);
+
   // Write Timing
   // Can be decreased from 8-15-8 to 0-0-1 with risk of stability loss
-  extTiming.AddressSetupTime = 8;
-  extTiming.AddressHoldTime = 15;
-  extTiming.DataSetupTime = 8;
-  extTiming.BusTurnAroundDuration = 0;
-  extTiming.CLKDivision = 16;
-  extTiming.DataLatency = 17;
-  extTiming.AccessMode = FSMC_ACCESS_MODE_A;
-
-  __HAL_RCC_FSMC_CLK_ENABLE();
+  extTiming.AddressSetupTime      =  8;
+  extTiming.AddressHoldTime       = 15;
+  extTiming.DataSetupTime         =  8;
+  extTiming.BusTurnAroundDuration =  0;
+  extTiming.CLKDivision           = 16;
+  extTiming.DataLatency           = 17;
+  extTiming.AccessMode            = FMC_OR_FSMC(ACCESS_MODE_A);
+
+  #ifdef STM32F446xx
+    __HAL_RCC_FMC_CLK_ENABLE();
+  #else
+    __HAL_RCC_FSMC_CLK_ENABLE();
+  #endif
 
   for (uint16_t i = 0; pinMap_FSMC[i].pin != NC; i++)
     pinmap_pinout(pinMap_FSMC[i].pin, pinMap_FSMC);
@@ -90,59 +101,54 @@ void TFT_FSMC::init() {
   controllerAddress = FSMC_BANK1_1;
   #ifdef PF0
     switch (nsBank) {
-      case FSMC_NORSRAM_BANK2: controllerAddress = FSMC_BANK1_2 ; break;
-      case FSMC_NORSRAM_BANK3: controllerAddress = FSMC_BANK1_3 ; break;
-      case FSMC_NORSRAM_BANK4: controllerAddress = FSMC_BANK1_4 ; break;
+      case FMC_OR_FSMC(NORSRAM_BANK2): controllerAddress = FSMC_BANK1_2; break;
+      case FMC_OR_FSMC(NORSRAM_BANK3): controllerAddress = FSMC_BANK1_3; break;
+      case FMC_OR_FSMC(NORSRAM_BANK4): controllerAddress = FSMC_BANK1_4; break;
     }
   #endif
 
   controllerAddress |= (uint32_t)pinmap_peripheral(digitalPinToPinName(TFT_RS_PIN), pinMap_FSMC_RS);
 
   HAL_SRAM_Init(&SRAMx, &timing, &extTiming);
 
+  __HAL_RCC_DMA2_CLK_ENABLE();
+
   #ifdef STM32F1xx
-    __HAL_RCC_DMA1_CLK_ENABLE();
-    DMAtx.Instance = DMA1_Channel1;
+    DMAtx.Instance                = DMA2_Channel1;
   #elif defined(STM32F4xx)
-    __HAL_RCC_DMA2_CLK_ENABLE();
-    DMAtx.Instance = DMA2_Stream0;
-    DMAtx.Init.Channel = DMA_CHANNEL_0;
-    DMAtx.Init.FIFOMode = DMA_FIFOMODE_ENABLE;
-    DMAtx.Init.FIFOThreshold = DMA_FIFO_THRESHOLD_FULL;
-    DMAtx.Init.MemBurst = DMA_MBURST_SINGLE;
-    DMAtx.Init.PeriphBurst = DMA_PBURST_SINGLE;
+    DMAtx.Instance                = DMA2_Stream0;
+    DMAtx.Init.Channel            = DMA_CHANNEL_0;
+    DMAtx.Init.FIFOMode           = DMA_FIFOMODE_ENABLE;
+    DMAtx.Init.FIFOThreshold      = DMA_FIFO_THRESHOLD_FULL;
+    DMAtx.Init.MemBurst           = DMA_MBURST_SINGLE;
+    DMAtx.Init.PeriphBurst        = DMA_PBURST_SINGLE;
   #endif
 
-  DMAtx.Init.Direction = DMA_MEMORY_TO_MEMORY;
-  DMAtx.Init.MemInc = DMA_MINC_DISABLE;
-  DMAtx.Init.PeriphDataAlignment = DMA_PDATAALIGN_HALFWORD;
-  DMAtx.Init.MemDataAlignment = DMA_MDATAALIGN_HALFWORD;
-  DMAtx.Init.Mode = DMA_NORMAL;
-  DMAtx.Init.Priority = DMA_PRIORITY_HIGH;
+  DMAtx.Init.Direction            = DMA_MEMORY_TO_MEMORY;
+  DMAtx.Init.MemInc               = DMA_MINC_DISABLE;
+  DMAtx.Init.PeriphDataAlignment  = DMA_PDATAALIGN_HALFWORD;
+  DMAtx.Init.MemDataAlignment     = DMA_MDATAALIGN_HALFWORD;
+  DMAtx.Init.Mode                 = DMA_NORMAL;
+  DMAtx.Init.Priority             = DMA_PRIORITY_HIGH;
 
   LCD = (LCD_CONTROLLER_TypeDef *)controllerAddress;
 }
 
 uint32_t TFT_FSMC::getID() {
-  uint32_t id;
   writeReg(0);
-  id = LCD->RAM;
-
-  if (id == 0)
-    id = readID(LCD_READ_ID);
-  if ((id & 0xFFFF) == 0 || (id & 0xFFFF) == 0xFFFF)
-    id = readID(LCD_READ_ID4);
+  uint32_t id = LCD->RAM;
+  if (id == 0) id = readID(LCD_READ_ID);
+  if ((id & 0xFFFF) == 0 || (id & 0xFFFF) == 0xFFFF) id = readID(LCD_READ_ID4);
   return id;
 }
 
-uint32_t TFT_FSMC::readID(const tft_data_t inReg) {
-  uint32_t id;
+uint32_t TFT_FSMC::readID(tft_data_t inReg) {
   writeReg(inReg);
-  id = LCD->RAM; // dummy read
+  uint32_t id = LCD->RAM; // dummy read
   id = inReg << 24;
   id |= (LCD->RAM & 0x00FF) << 16;
   id |= (LCD->RAM & 0x00FF) << 8;
-  id |= LCD->RAM & 0x00FF;
+  id |= (LCD->RAM & 0x00FF);
   return id;
 }
 
@@ -155,7 +161,9 @@ bool TFT_FSMC::isBusy() {
     #define __IS_DMA_CONFIGURED(__HANDLE__)   ((__HANDLE__)->Instance->PAR != 0)
   #endif
 
-  if (!__IS_DMA_CONFIGURED(&DMAtx)) return false;
+  #ifdef __IS_DMA_CONFIGURED
+    if (!__IS_DMA_CONFIGURED(&DMAtx)) return false;
+  #endif
 
   // Check if DMA transfer error or transfer complete flags are set
   if ((__HAL_DMA_GET_FLAG(&DMAtx, __HAL_DMA_GET_TE_FLAG_INDEX(&DMAtx)) == 0) && (__HAL_DMA_GET_FLAG(&DMAtx, __HAL_DMA_GET_TC_FLAG_INDEX(&DMAtx)) == 0)) return true;
@@ -174,8 +182,6 @@ void TFT_FSMC::transmitDMA(uint32_t memoryIncrease, uint16_t *data, uint16_t cou
   DMAtx.Init.PeriphInc = memoryIncrease;
   HAL_DMA_Init(&DMAtx);
   HAL_DMA_Start(&DMAtx, (uint32_t)data, (uint32_t)&(LCD->RAM), count);
-
-  TERN_(TFT_SHARED_IO, while (isBusy()));
 }
 
 void TFT_FSMC::transmit(uint32_t memoryIncrease, uint16_t *data, uint16_t count) {

Marlin/src/HAL/STM32/tft/tft_fsmc.h

@@ -28,11 +28,7 @@
 #elif defined(STM32F4xx)
   #include "stm32f4xx_hal.h"
 #else
-  #error "FSMC TFT is currently only supported on STM32F1 and STM32F4 hardware."
-#endif
-
-#ifndef HAL_SRAM_MODULE_ENABLED
-  #error "SRAM module disabled for the STM32 framework (HAL_SRAM_MODULE_ENABLED)! Please consult the development team."
+  #error "FSMC/FMC TFT is currently only supported on STM32F1 and STM32F4 hardware."
 #endif
 
 #ifndef LCD_READ_ID
@@ -55,14 +51,20 @@ typedef struct {
   __IO tft_data_t RAM;
 } LCD_CONTROLLER_TypeDef;
 
+#ifdef STM32F446xx
+  #define FMC_OR_FSMC(N) _CAT(FMC_, N)
+#else
+  #define FMC_OR_FSMC(N) _CAT(FSMC_, N)
+#endif
+
 class TFT_FSMC {
   private:
     static SRAM_HandleTypeDef SRAMx;
     static DMA_HandleTypeDef DMAtx;
 
     static LCD_CONTROLLER_TypeDef *LCD;
 
-    static uint32_t readID(const tft_data_t reg);
+    static uint32_t readID(tft_data_t inReg);
     static void transmit(tft_data_t data) { LCD->RAM = data; __DSB(); }
     static void transmit(uint32_t memoryIncrease, uint16_t *data, uint16_t count);
     static void transmitDMA(uint32_t memoryIncrease, uint16_t *data, uint16_t count);
@@ -94,7 +96,11 @@ class TFT_FSMC {
 #ifdef STM32F1xx
   #define FSMC_PIN_DATA   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, AFIO_NONE)
 #elif defined(STM32F4xx)
-  #define FSMC_PIN_DATA   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FSMC)
+  #ifdef STM32F446xx
+    #define FSMC_PIN_DATA   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FMC)
+  #else
+    #define FSMC_PIN_DATA   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF12_FSMC)
+  #endif
   #define FSMC_BANK1_1    0x60000000U
   #define FSMC_BANK1_2    0x64000000U
   #define FSMC_BANK1_3    0x68000000U
@@ -104,35 +110,35 @@ class TFT_FSMC {
 #endif
 
 const PinMap pinMap_FSMC[] = {
-  {PD_14,  FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D00
-  {PD_15,  FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D01
-  {PD_0,   FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D02
-  {PD_1,   FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D03
-  {PE_7,   FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D04
-  {PE_8,   FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D05
-  {PE_9,   FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D06
-  {PE_10,  FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D07
+  {PD_14,  FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D00
+  {PD_15,  FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D01
+  {PD_0,   FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D02
+  {PD_1,   FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D03
+  {PE_7,   FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D04
+  {PE_8,   FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D05
+  {PE_9,   FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D06
+  {PE_10,  FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D07
   #if DISABLED(TFT_INTERFACE_FSMC_8BIT)
-    {PE_11,  FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D08
-    {PE_12,  FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D09
-    {PE_13,  FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D10
-    {PE_14,  FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D11
-    {PE_15,  FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D12
-    {PD_8,   FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D13
-    {PD_9,   FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D14
-    {PD_10,  FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_D15
+    {PE_11,  FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D08
+    {PE_12,  FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D09
+    {PE_13,  FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D10
+    {PE_14,  FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D11
+    {PE_15,  FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D12
+    {PD_8,   FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D13
+    {PD_9,   FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D14
+    {PD_10,  FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_D15
   #endif
-  {PD_4,   FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NOE
-  {PD_5,   FSMC_NORSRAM_DEVICE, FSMC_PIN_DATA}, // FSMC_NWE
+  {PD_4,   FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_NOE
+  {PD_5,   FMC_OR_FSMC(NORSRAM_DEVICE), FSMC_PIN_DATA}, // FSMC_NWE
   {NC,    NP,    0}
 };
 
 const PinMap pinMap_FSMC_CS[] = {
-  {PD_7,  (void *)FSMC_NORSRAM_BANK1, FSMC_PIN_DATA}, // FSMC_NE1
+  {PD_7,  (void *)FMC_OR_FSMC(NORSRAM_BANK1), FSMC_PIN_DATA}, // FSMC_NE1
   #ifdef PF0
-    {PG_9,  (void *)FSMC_NORSRAM_BANK2, FSMC_PIN_DATA}, // FSMC_NE2
-    {PG_10, (void *)FSMC_NORSRAM_BANK3, FSMC_PIN_DATA}, // FSMC_NE3
-    {PG_12, (void *)FSMC_NORSRAM_BANK4, FSMC_PIN_DATA}, // FSMC_NE4
+    {PG_9,  (void *)FMC_OR_FSMC(NORSRAM_BANK2), FSMC_PIN_DATA}, // FSMC_NE2
+    {PG_10, (void *)FMC_OR_FSMC(NORSRAM_BANK3), FSMC_PIN_DATA}, // FSMC_NE3
+    {PG_12, (void *)FMC_OR_FSMC(NORSRAM_BANK4), FSMC_PIN_DATA}, // FSMC_NE4
   #endif
   {NC,    NP,    0}
 };

Marlin/src/core/boards.h

@@ -459,7 +459,7 @@
 #define BOARD_OPULO_LUMEN_REV4        5242  // Opulo Lumen PnP Controller REV4 (STM32F407VE / STM32F407VG)
 #define BOARD_FYSETC_SPIDER_KING407   5243  // FYSETC Spider King407 (STM32F407ZG)
 #define BOARD_MKS_SKIPR_V1            5244  // MKS SKIPR v1.0 all-in-one board (STM32F407VE)
-#define BOARD_TRONXY_V10              5245  // TRONXY V10 (STM32F446ZE)
+#define BOARD_TRONXY_CXY_446_V10      5245  // TRONXY CXY-446-V10-220413/CXY-V6-191121 (STM32F446ZE)
 #define BOARD_CREALITY_F401RE         5246  // Creality CR4NS200141C13 (STM32F401RE) as found in the Ender-5 S1
 #define BOARD_BLACKPILL_CUSTOM        5247  // Custom board based on STM32F401CDU6.
 #define BOARD_I3DBEEZ9_V1             5248  // I3DBEEZ9 V1 (STM32F407ZG)

Marlin/src/pins/pins.h

@@ -806,8 +806,8 @@
   #include "stm32f4/pins_FYSETC_SPIDER_KING407.h"   // STM32F4                              env:FYSETC_SPIDER_KING407
 #elif MB(MKS_SKIPR_V1)
   #include "stm32f4/pins_MKS_SKIPR_V1_0.h"          // STM32F4                              env:mks_skipr_v1 env:mks_skipr_v1_nobootloader
-#elif MB(TRONXY_V10)
-  #include "stm32f4/pins_TRONXY_V10.h"              // STM32F4                              env:STM32F446_tronxy
+#elif MB(TRONXY_CXY_446_V10)
+  #include "stm32f4/pins_TRONXY_CXY_446_V10.h"      // STM32F4                              env:TRONXY_CXY_446_V10 env:TRONXY_CXY_446_V10_usb_flash_drive
 #elif MB(CREALITY_F401RE)
   #include "stm32f4/pins_CREALITY_F401.h"           // STM32F4                              env:STM32F401RE_creality
 #elif MB(BLACKPILL_CUSTOM)
@@ -956,6 +956,7 @@
   #define BOARD_LINUX_RAMPS             99926
   #define BOARD_BTT_MANTA_M4P_V1_0      99927
   #define BOARD_VAKE403D                99928
+  #define BOARD_TRONXY_V10              99929
 
   #if MB(MKS_13)
     #error "BOARD_MKS_13 is now BOARD_MKS_GEN_13. Please update your configuration."
@@ -1015,6 +1016,8 @@
     #error "BOARD_LINUX_RAMPS is now BOARD_SIMULATED. Please update your configuration."
   #elif MB(BTT_MANTA_M4P_V1_0)
     #error "BOARD_BTT_MANTA_M4P_V1_0 is now BOARD_BTT_MANTA_M4P_V2_1. Please update your configuration."
+  #elif MB(BOARD_TRONXY_V10)
+    #error "BOARD_TRONXY_V10 is now BOARD_TRONXY_CXY_446_V10. Please update your configuration."
   #elif MB(VAKE403D)
     #error "BOARD_VAKE403D is no longer supported in Marlin."
   #elif defined(MOTHERBOARD)
@@ -1053,6 +1056,7 @@
   #undef BOARD_LINUX_RAMPS
   #undef BOARD_BTT_MANTA_M4P_V1_0
   #undef BOARD_VAKE403D
+  #undef BOARD_TRONXY_V10
 
 #endif