[config] Enable AXP15060 regulator

.github/workflows/build.yml

@@ -0,0 +1,77 @@
+name: Star64 kernel build
+on: [workflow_dispatch, push]
+concurrency:
+  group: ${{ github.workflow }}-${{ github.ref }}
+  cancel-in-progress: true
+permissions: {}
+defaults:
+  run:
+    shell: sh
+jobs:
+  build:
+    # https://github.com/actions/virtual-environments
+    runs-on: ubuntu-22.04
+    env:
+      CROSS_COMPILE: 'riscv64-linux-gnu-'
+      ARCH: 'riscv'
+    steps:
+    - name: Setup tmpfs
+      run: sudo mount -t tmpfs -o "noatime,lazytime,uid=$(id -u),size=3G" tmpfs "$GITHUB_WORKSPACE"
+    - uses: actions/checkout@v4
+    - name: Install build dependencies
+      run: |
+        sudo apt-get -q update
+        sudo DEBIAN_FRONTEND=noninteractive apt-get --no-install-recommends -qq dist-upgrade
+        sudo DEBIAN_FRONTEND=noninteractive apt-get --no-install-recommends -qq install make gcc libc6-dev flex bison gcc-riscv64-linux-gnu bc libssl-dev
+    - name: Build Linux
+      run: |
+        > .scmversion # Avoid Git commit version suffix
+        mv -v dietpi_star64_defconfig arch/riscv/configs/
+        make dietpi_star64_defconfig
+        make -j$(nproc)
+        make install INSTALL_PATH='linux-image-star64/boot'
+        make dtbs_install INSTALL_DTBS_PATH='linux-image-star64/usr/lib/linux-image-star64'
+        find linux-image-star64/usr/lib/linux-image-star64 -mindepth 1 ! \( -name 'starfive' -o -name 'jh7110-pine64-star64.dtb' \) -exec rm -Rfv {} +
+        make modules_install INSTALL_MOD_PATH='linux-image-star64'
+        rm linux-image-star64/lib/modules/*/build linux-image-star64/lib/modules/*/source
+        # https://github.com/starfive-tech/buildroot/blob/JH7110_VisionFive2_devel/package/starfive/starfive-firmware/starfive-firmware.mk
+        mkdir -p linux-image-star64/lib/firmware
+        cd linux-image-star64/lib/firmware
+        curl -sSfO 'https://raw.githubusercontent.com/starfive-tech/buildroot/JH7110_VisionFive2_devel/package/starfive/starfive-firmware/ap6256-bluetooth/BCM4345C5.hcd'
+        curl -sSfO 'https://raw.githubusercontent.com/starfive-tech/buildroot/JH7110_VisionFive2_devel/package/starfive/starfive-firmware/ap6256-sdio-wifi/fw_bcm43456c5_ag.bin'
+        curl -sSfO 'https://raw.githubusercontent.com/starfive-tech/buildroot/JH7110_VisionFive2_devel/package/starfive/starfive-firmware/ap6256-sdio-wifi/nvram_ap6256.txt'
+        curl -sSfO 'https://raw.githubusercontent.com/starfive-tech/buildroot/JH7110_VisionFive2_devel/package/starfive/starfive-firmware/rtl8852bu-bluetooth/rtl8852bu_config'
+        curl -sSfO 'https://raw.githubusercontent.com/starfive-tech/buildroot/JH7110_VisionFive2_devel/package/starfive/starfive-firmware/rtl8852bu-bluetooth/rtl8852bu_fw'
+        curl -sSfO 'https://raw.githubusercontent.com/starfive-tech/buildroot/JH7110_VisionFive2_devel/package/starfive/starfive-firmware/ECR6600U-usb-wifi/ECR6600U_transport.bin'
+        svn export 'https://github.com/starfive-tech/buildroot/branches/JH7110_VisionFive2_devel/package/starfive/starfive-firmware/aic8800-usb-wifi/aic8800'
+        svn export 'https://github.com/starfive-tech/buildroot/branches/JH7110_VisionFive2_devel/package/starfive/starfive-firmware/aic8800-usb-wifi/aic8800DC'
+        cd ../../..
+        find linux-image-star64 -type f \( -path linux-image-star64/DEBIAN -prune \) -exec chmod 0644 {} +
+        find linux-image-star64 -type d -exec chmod 0755 {} +
+    - name: Build package
+      run: |
+        echo 'Obtaining kernel and package version ...'
+        kernelversion=$(make kernelversion)
+        curl -fO 'https://dietpi.com/downloads/binaries/linux-image-star64.deb'
+        cur_version=$(dpkg-deb -f linux-image-star64.deb Version)
+        rm linux-image-star64.deb
+        cur_suffix=${cur_version#*-dietpi}
+        echo "Current package version is : $cur_version"
+        echo "New kernel version is      : $kernelversion"
+        [ "$kernelversion-dietpi$cur_suffix" = "$cur_version" ] && version="$kernelversion-dietpi$((cur_suffix+1))" || version="$kernelversion-dietpi1"
+        echo "New package version will be: $version"
+        sed -i "s/VERSION/$kernelversion/g" linux-image-star64/boot/extlinux/extlinux.conf linux-image-star64/DEBIAN/p*
+        find linux-image-star64 ! \( -path linux-image-star64/DEBIAN -prune \) -type f -exec md5sum {} + | sed 's|linux-image-star64/||' > linux-image-star64/DEBIAN/md5sums
+        sed -i -e "s/VERSION/$version/" -e "s/DATE/$(date -u '+%a, %d %b %Y %T %z')/" -e "s/SIZE/$(du -sk 'linux-image-star64' | mawk '{print $1}')/" linux-image-star64/DEBIAN/control
+        sudo chown -R 0:0 linux-image-star64
+        dpkg-deb -b -Zxz -z9 -Sextreme linux-image-star64
+        sudo rm -R linux-image-star64
+    - name: Upload
+      run: |
+        mkdir -p ~/.ssh
+        umask 377
+        echo '${{ secrets.KNOWN_HOSTS }}' > ~/.ssh/known_hosts
+        echo '${{ secrets.SSH_KEY }}' > ~/.ssh/id_ed25519
+        curl -T 'linux-image-star64.deb' --key ~/.ssh/id_ed25519 '${{ secrets.UPLOAD_URL }}all/'
+        curl 'https://api.cloudflare.com/client/v4/zones/${{ secrets.CF_ZONE }}/purge_cache' -H 'Authorization: Bearer ${{ secrets.CF_TOKEN }}' -H 'Content-Type: application/json' \
+        --data '{"files":["https://dietpi.com/downloads/binaries/testing/","https://dietpi.com/downloads/binaries/testing/linux-image-star64.deb"]}'

.gitignore

@@ -10,7 +10,7 @@
 #
 # Normal rules (sorted alphabetically)
 #
-.*
+#.*
 *.a
 *.asn1.[ch]
 *.bin

Documentation/devicetree/bindings/clock/starfive,jh7110-clk-isp.yaml

@@ -0,0 +1,97 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh7110-clk-isp.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 ISP Clock Generator
+
+maintainers:
+  - Xingyu Wu <xingyu.wu@starfivetech.com>
+
+description: |
+  The JH7110 SoC provides clock generator in various system controller (*crg)
+  hardware modules. The clock generator provides clock to the targeted domain
+  in the SoC. The clock generator node is defined as a child node of its
+  system controller node.
+
+properties:
+  compatible:
+    const: starfive,jh7110-clk-isp
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: DVP clock
+      - description: ISP CORE_2X clock
+      - description: ISP AXI clock
+      - description: NOC_BUS ISP clock
+
+  clock-names:
+    items:
+      - const: u0_dom_isp_top_clk_dom_isp_top_clk_dvp
+      - const: u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x
+      - const: u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi
+      - const: u0_sft7110_noc_bus_clk_isp_axi
+
+  resets:
+    items:
+      - description: ISP reset
+      - description: ISP AXI reset
+      - description: NOC_BUS ISP reset
+
+  reset-names:
+    items:
+      - const: rst_isp_top_n
+      - const: rst_isp_top_axi
+      - const: rst_isp_noc_bus_n
+
+  '#clock-cells':
+    const: 1
+    description:
+      See <dt-bindings/clock/starfive-jh7110-clk-isp.h> for valid indices.
+
+  power-domains:
+    maxItems: 1
+    description:
+      ISP domain power
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - '#clock-cells'
+  - power-domains
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
+    #include <dt-bindings/clock/starfive-jh7110-clk-isp.h>
+    clkisp: clock-controller@19810000 {
+        compatible = "starfive,jh7110-clk-isp";
+        reg = <0x0 0x19810000 0x0 0x10000>;
+        reg-names = "isp";
+        #clock-cells = <1>;
+        clocks = <&clkgen JH7110_ISP_TOP_CLK_DVP>,
+                 <&clkgen JH7110_ISP_TOP_CLK_ISPCORE_2X>,
+                 <&clkgen JH7110_ISP_TOP_CLK_ISP_AXI>,
+                 <&clkgen JH7110_NOC_BUS_CLK_ISP_AXI>;
+        clock-names = "u0_dom_isp_top_clk_dom_isp_top_clk_dvp",
+                      "u0_dom_isp_top_clk_dom_isp_top_clk_ispcore_2x",
+                      "u0_dom_isp_top_clk_dom_isp_top_clk_isp_axi",
+                      "u0_sft7110_noc_bus_clk_isp_axi";
+        resets = <&rstgen RSTN_U0_DOM_ISP_TOP_N>,
+                 <&rstgen RSTN_U0_DOM_ISP_TOP_AXI>,
+                 <&rstgen RSTN_U0_NOC_BUS_ISP_AXI_N>;
+        reset-names = "rst_isp_top_n", "rst_isp_top_axi",
+                      "rst_isp_noc_bus_n";
+        power-domains = <&pwrc JH7110_PD_ISP>;
+    };

Documentation/devicetree/bindings/clock/starfive,jh7110-clk-vout.yaml

@@ -0,0 +1,94 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh7110-clk-vout.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 VOUT Clock Generator
+
+maintainers:
+  - Xingyu Wu <xingyu.wu@starfivetech.com>
+
+description: |
+  The JH7110 SoC provides clock generator in various system controller (*crg)
+  hardware modules. The clock generator provides clock to the targeted domain
+  in the SoC. The clock generator node is defined as a child node of its
+  system controller node.
+
+properties:
+  compatible:
+    const: starfive,jh7110-clk-vout
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: external HDMI clock
+      - description: external MIPI Escape mode Receive clock
+      - description: external MIPI high-speed Transmit clock
+      - description: VOUT SRC clock
+      - description: VOUT AHB clock
+
+  clock-names:
+    items:
+      - const: hdmitx0_pixelclk
+      - const: mipitx_dphy_rxesc
+      - const: mipitx_dphy_txbytehs
+      - const: vout_src
+      - const: vout_top_ahb
+
+  resets:
+    items:
+      - description: VOUT SRC reset
+
+  reset-names:
+    items:
+      - const: vout_src
+
+  '#clock-cells':
+    const: 1
+    description:
+      See <dt-bindings/clock/starfive-jh7110-vout.h> for valid indices.
+
+  power-domains:
+    maxItems: 1
+    description:
+      VOUT domain power
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - clocks
+  - clock-names
+  - resets
+  - reset-names
+  - '#clock-cells'
+  - power-domains
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/starfive-jh7110-clkgen.h>
+    #include <dt-bindings/clock/starfive-jh7110-vout.h>
+    clkvout: clock-controller@295C0000 {
+        compatible = "starfive,jh7110-clk-vout";
+        reg = <0x0 0x295C0000 0x0 0x10000>;
+        reg-names = "vout";
+        clocks = <&hdmitx0_pixelclk>,
+                 <&mipitx_dphy_rxesc>,
+                 <&mipitx_dphy_txbytehs>,
+                 <&clkgen JH7110_VOUT_SRC>,
+                 <&clkgen JH7110_VOUT_TOP_CLK_VOUT_AHB>;
+        clock-names = "hdmitx0_pixelclk",
+                      "mipitx_dphy_rxesc",
+                      "mipitx_dphy_txbytehs",
+                      "vout_src",
+                      "vout_top_ahb";
+        resets = <&rstgen RSTN_U0_DOM_VOUT_TOP_SRC>;
+        reset-names = "vout_src";
+        #clock-cells = <1>;
+        power-domains = <&pwrc JH7110_PD_VOUT>;
+    };

Documentation/devicetree/bindings/clock/starfive,jh7110-clkgen.yaml

@@ -0,0 +1,106 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/starfive,jh7110-clkgen.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: StarFive JH7110 Clock Generator
+
+maintainers:
+  - Xingyu Wu <xingyu.wu@starfivetech.com>
+
+description: |
+  The JH7110 SoC provides clock generator in various system controller (*crg)
+  hardware modules. The clock generator provides clock to the targeted domain
+  in the SoC. The clock generator node is defined as a child node of its
+  system controller node.
+
+properties:
+  compatible:
+    const: starfive,jh7110-clkgen
+
+  reg:
+    maxItems: 3
+
+  clocks:
+    items:
+      - description: Main clock source
+      - description: external RMII clock for GMAC1
+      - description: external RGMII clock for GMAC1
+      - description: I2S Transmit serial clock
+      - description: I2S Transmit frame sync clock
+      - description: I2S Receive serial clock
+      - description: I2S Receive frame sync clock
+      - description: external TDM clock
+      - description: external Master clock
+      - description: inner JTAG TCK clock
+      - description: BIST clock
+      - description: RTC clock
+      - description: external RMII clock for GMAC0
+      - description: external RGMII clock for GMAC0
+
+  clock-names:
+    items:
+      - const: osc
+      - const: gmac1_rmii_refin
+      - const: gmac1_rgmii_rxin
+      - const: i2stx_bclk_ext
+      - const: i2stx_lrck_ext
+      - const: i2srx_bclk_ext
+      - const: i2srx_lrck_ext
+      - const: tdm_ext
+      - const: clk_mclk_ext
+      - const: jtag_tck_inner
+      - const: clk_bist_apb
+      - const: clk_rtc
+      - const: gmac0_rmii_refin
+      - const: gmac0_rgmii_rxin
+
+  '#clock-cells':
+    const: 1
+    description:
+      See <dt-bindings/clock/starfive-jh7110-clkgen.h> for valid indices.
+
+  starfive,sys-syscon:
+    description:
+      PLL clock configuration registers.
+
+required:
+  - compatible
+  - reg
+  - reg-names
+  - clocks
+  - clock-names
+  - '#clock-cells'
+  - starfive,sys-syscon
+
+additionalProperties: false
+
+examples:
+  - |
+    clock-controller {
+        compatible = "starfive,jh7110-clkgen";
+        reg = <0x0 0x13020000 0x0 0x10000>,
+              <0x0 0x10230000 0x0 0x10000>,
+              <0x0 0x17000000 0x0 0x10000>;
+        reg-names = "sys", "stg", "aon";
+        clocks = <&osc>, <&gmac1_rmii_refin>,
+                 <&gmac1_rgmii_rxin>,
+                 <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
+                 <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
+                 <&tdm_ext>, <&mclk_ext>,
+                 <&jtag_tck_inner>, <&bist_apb>,
+                 <&clk_rtc>,
+                 <&gmac0_rmii_refin>, <&gmac0_rgmii_rxin>;
+        clock-names = "osc", "gmac1_rmii_refin",
+                      "gmac1_rgmii_rxin",
+                      "i2stx_bclk_ext", "i2stx_lrck_ext",
+                      "i2srx_bclk_ext", "i2srx_lrck_ext",
+                      "tdm_ext", "mclk_ext",
+                      "jtag_tck_inner", "bist_apb",
+                      "clk_rtc",
+                      "gmac0_rmii_refin", "gmac0_rgmii_rxin";
+        #clock-cells = <1>;
+        starfive,sys-syscon = <&sys_syscon 0x18 0x1c
+                  0x20 0x24 0x28 0x2c 0x30 0x34>;
+    };