re-added riscv-vector-tests option to simx

MichaelJSr · Oct 7, 2024 · c3ae793 · c3ae793
1 parent d497c95
commit c3ae793
Showing 1 changed file with 5 additions and 1 deletion.
diff --git a/sim/simx/main.cpp b/sim/simx/main.cpp
@@ -36,6 +36,7 @@ uint32_t num_threads = NUM_THREADS;
 uint32_t num_warps = NUM_WARPS;
 uint32_t num_cores = NUM_CORES;
 bool showStats = false;
+bool riscv_test = false;
 const char* program = nullptr;
 
 static void parse_args(int argc, char **argv) {
@@ -54,6 +55,9 @@ static void parse_args(int argc, char **argv) {
       case 's':
         showStats = true;
         break;
+      case 'r':
+        riscv_test = true;
+        break;
     	case 'h':
       	show_usage();
       	exit(0);
@@ -121,5 +125,5 @@ int main(int argc, char **argv) {
     ram.read(&exitcode, (IO_MPM_ADDR + 8), 4);
   }
 
-  return exitcode;
+  return exitcode if not riscv_test else (1 - exitcode);
 }