First draft for pipelining

SRC/components/array_t.vhd

@@ -24,10 +24,13 @@ PACKAGE array_t IS
 	constant NBITS: natural := 32;	-- input size
 	constant A_WIDTH: natural := 24;
 	constant B_WIDTH: natural := 23;
-	constant NLEVEL : natural := 6; 
+	constant NLEVEL : natural := 8; 	--Pipeline included
+	constant ELEM_ADDER : natrual := 0;
+	constant ELEM_REG : natrual := 1;
 	TYPE net_mat is array (natural range <>) of array32_t(0 to A_WIDTH-1);	--matrix of wire, each entry has maximum 3 entries and there is NIN entries
-	TYPE vect3 is array (0 to 4) of natural;	--number of element, then shifts numbers
-	TYPE matrix_vect is array (natural range <>) of vect3;
+	TYPE vect5 is array (0 to 4) of natural;	--number of element, then shifts numbers
+	TYPE vect2 is array (0 to 1) of natural
+	TYPE matrix_vect is array (natural range <>) of vect5;
 	constant a_shift_arr: matrix_vect(0 to (NIN/2)-1) := (
 		(2,1,0,0,0),
 		(3,4,3,0,2),
@@ -42,11 +45,23 @@ PACKAGE array_t IS
 		(3,8,6,0,7),
 		(3,10,9,2,10)
 		);
-	constant a_adder_index: array_int_t(0 to NLEVEL-2) := (
-	   12, 6, 3, 1, 1
+	constant a_elem_index: vect2(0 to NLEVEL-2) := (
+		(12, 0),
+		(6, 0),
+		(0, 6),
+		(3, 0),
+		(1, 0),
+		(0, 2),
+		(1, 0)
 	   );		
 
-	constant b_adder_index: array_int_t(0 to NLEVEL-2) := (
-	   11, 6, 3, 1, 1
+	constant b_elem_index: vect2(0 to NLEVEL-2) := (
+		(11, 0),
+		(6, 0),
+		(0, 6),
+		(3, 0),
+		(1, 0),
+		(0, 2),
+		(1, 0)
 	   );
 END array_t;

SRC/fir_sol/comb_part.vhd

@@ -8,6 +8,8 @@ use work.array_t.all;
 
 entity comb_part is
 	port(
+		signal Reset : in  STD_LOGIC;
+        signal Clk : in  STD_LOGIC;
 		signal comb_a_in : in array32_t(0 to NIN-1);
 		signal comb_b_in : in array32_t(0 to NIN-2);
 		signal comb_out : out STD_LOGIC_VECTOR (NBITS-1 downto 0)
@@ -24,9 +26,17 @@ architecture Structural of comb_part is
         );
 	end component;
 
+	component reg 
+    Port ( Reset : in  STD_LOGIC;
+           Clk : in  STD_LOGIC;
+           Load : in  STD_LOGIC;
+           Din : in  STD_LOGIC_VECTOR (31 downto 0);
+           Dout : out  STD_LOGIC_VECTOR (31 downto 0));
+	end component;
+
 	signal a_web : net_mat(0 to NLEVEL-1); --there is 8 different level of wire to pass from entries to single result from a side
 	signal b_web : net_mat(0 to NLEVEL-1); --there is 8 different level of wire to pass from entries to single result from b side
-  signal temp_out : STD_LOGIC_VECTOR (NBITS-1 downto 0); 
+  	signal temp_out : STD_LOGIC_VECTOR (NBITS-1 downto 0); 
 
 begin
 
@@ -40,13 +50,16 @@ begin
 	end generate;
 
 
-	a_3: for k in 0 to NLEVEL-2 generate					--generate adders for each level	
-		a_4: for l in 0 to a_adder_index(k)-1 generate
+	a_3: for k in 0 to NLEVEL-2 generate	--generate adders or pipeline for each level	
+		a_4: for l in 0 to a_elem_index(k)(ELEM_ADDER)-1 generate
 			a_add: adder port map(a_web(k)(2*l),a_web(k)(2*l +1),a_web(k+1)(l));
 		end generate a_4;
-		a_5: if k = 3 generate		--when number of wire is odd, no need for adder
-			a_web(k+1)(a_adder_index(k)) <= a_web(k)(2*a_adder_index(k));
+		a_5: if k = 4 generate		--when number of wire is odd, no need for adder but one wire need to be transmited
+			a_web(k+1)(a_elem_index(k)(ELEM_ADDER)) <= a_web(k)(2*a_elem_index(k)(ELEM_ADDER));
 		end generate a_5;
+		ap_1: for m in 0 to a_elem_index(k)(ELEM_REG)-1 generate	--register for pipeline
+			a_reg: reg port map(Reset, Clk, '1', a_web(k)(m),a_web(k+1)(m));
+		end generate;
 	end generate a_3;
 
 
@@ -63,12 +76,15 @@ begin
 
 
 	b_3: for k in 0 to NLEVEL-2 generate					--generate adders for each level	
-		b_4: for l in 0 to b_adder_index(k)-1 generate
+		b_4: for l in 0 to b_elem_index(k)(ELEM_ADDER)-1 generate
 			 b_add: adder port map(b_web(k)(2*l),b_web(k)(2*l +1),b_web(k+1)(l));
 		end generate b_4;
-		b_5: if (k = 3 OR k = 0) generate		--when number of wire is odd, no need for adder
-			b_web(k+1)(b_adder_index(k)) <= b_web(k)(2*b_adder_index(k));
+		b_5: if (k = 4 OR k = 0) generate		--when number of wire is odd, no need for adder
+			b_web(k+1)(b_elem_index(k)(ELEM_ADDER)) <= b_web(k)(2*b_elem_index(k)(ELEM_ADDER));
 		end generate b_5;
+		bp_1: for m in 0 to b_elem_index(k)(ELEM_REG)-1 generate	--register for pipeline
+			b_reg: reg port map(Reset, Clk, '1', b_web(k)(m),b_web(k+1)(m));
+		end generate;
 	end generate b_3;
 
 

SRC/fir_sol/iir_sol.vhd

@@ -28,6 +28,8 @@ architecture Structural of iir_sol is
 
 	component comb_part
 	port(
+		signal Reset : in  STD_LOGIC;
+        signal Clk : in  STD_LOGIC;
 		signal comb_a_in : in array32_t(0 to NIN-1);
 		signal comb_b_in : in array32_t(0 to NIN-2);
 		signal comb_out : out STD_LOGIC_VECTOR (NBITS-1 downto 0)
@@ -44,9 +46,7 @@ begin
 		regi2: reg port map(Reset,Clk,'1',reg_sig(i+1),reg_sig(i));	
 	end generate;
 
-	comb: comb_part port map(Input,reg_sig(0 to NIN-2),reg_sig(NIN-1));
-
-test
+	comb: comb_part port map(Reset, Clk, Input,reg_sig(0 to NIN-2),reg_sig(NIN-1));
 
 end Structural;