Added comments and cleanup

SRC/components/array_t.vhd

@@ -1,3 +1,8 @@
+--EPFL
+--DTIS PROJECT
+--Michael Roy
+--December 2012
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -20,23 +25,27 @@ PACKAGE array_t IS
 		x"00000003"
 	);
 
-	constant NIN: natural := 10;		--number of inputs
-	constant NBITS: natural := 32;	-- input size
-	constant A_WIDTH: natural := 24;
-	constant B_WIDTH: natural := 23;
-	constant NLEVEL_A : natural := 9; 	--Pipeline included
-	constant NLEVEL_B : natural := 11; 	--Pipeline included
-	constant ELEM_ADDER : natural := 0;	--Alias
+
+	--Here are all the defined use in other files (useful to easily tweak configuration)
+
+
+	constant NIN: natural := 10;					--Number of inputs (A side)
+	constant NBITS: natural := 32;					--Input width
+	constant A_WIDTH: natural := 24;				--Width of A size after expansion for shifting
+	constant B_WIDTH: natural := 23;				--Same for B side
+	constant NLEVEL_A : natural := 9; 				--Number of levels needed to sum in a tree all inputs from A side (pipeline included)
+	constant NLEVEL_B : natural := 11; 				--Same for B side
+	constant ELEM_ADDER : natural := 0;				--Alias to have more understandable names
 	constant ELEM_REG : natural := 1;
-	constant NPIPE : natural := 3;		--Number of pipelining
-	constant N_DIRECT_JUMP : natural := 7;	--Feedback need to be send to other level in order to avoid delay induced by pipelines
-	TYPE net_mat is array (natural range <>) of array32_t(0 to A_WIDTH-1);	--matrix of wire, each entry has maximum 3 entries and there is NIN entries
-	TYPE vect5 is array (0 to 4) of natural;	--number of element, then shifts numbers
+	constant NPIPE : natural := 3;					--Number of pipelining
+	constant N_DIRECT_JUMP : natural := 7;			--Feedback need to be send to lower level in order to avoid delay induced by pipelines
+	TYPE net_mat is array (natural range <>) of array32_t(0 to A_WIDTH-1);	--Matrix of wire for adding tree, each entry is expanded in maximum 3 shifts, and there is NIN entries
+	TYPE vect5 is array (0 to 4) of natural;		
 	TYPE vect2 is array (0 to 1) of natural;
 	TYPE matrix_vect2 is array (natural range <>) of vect2;
 	TYPE matrix_vect5 is array (natural range <>) of vect5;
 	constant a_shift_arr: matrix_vect5(0 to (NIN/2)-1) := (
-		(2,1,0,0,0),
+		(2,1,0,0,0),			--Number of shifts, shifts values (2 or 3) and index in wire matrix
 		(3,4,3,0,2),
 		(2,6,5,0,5),
 		(2,8,7,0,7),
@@ -49,7 +58,7 @@ PACKAGE array_t IS
 		(3,8,6,0,7),
 		(3,10,9,2,10)
 		);
-	constant a_elem_index: matrix_vect2(0 to NLEVEL_A-2) := (
+	constant a_elem_index: matrix_vect2(0 to NLEVEL_A-2) := (		--Index of adding tree: number of adders and number of registers
 		(12, 0),
 		(0, 12),	--Pipeline
 		(6, 0),
@@ -73,7 +82,7 @@ PACKAGE array_t IS
 		(1, 0)
 	   );
 
-	constant feedb_jump_index: matrix_vect2(0 to N_DIRECT_JUMP-1) := (
+	constant feedb_jump_index: matrix_vect2(0 to N_DIRECT_JUMP-1) := (		--Index for feedback shortcut (to balance delay induced by pipelines)
 		(9, 1),
 		(10, 1),
 		(6, 2),

SRC/fir_sol/comb_part.vhd

@@ -1,3 +1,8 @@
+--EPFL
+--DTIS PROJECT
+--Michael Roy
+--December 2012
+
 library ieee;
 use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
@@ -34,66 +39,72 @@ architecture Structural of comb_part is
            Dout : out  STD_LOGIC_VECTOR (31 downto 0));
 	end component;
 
-	signal a_web : net_mat(0 to NLEVEL_A-1); --there is 8 different level of wire to pass from entries to single result from a side
-	signal b_web : net_mat(0 to NLEVEL_B-1); --there is 8 different level of wire to pass from entries to single result from b side
+	signal a_web : net_mat(0 to NLEVEL_A-1); 							--There is NLEVEL_A different level of wire to reduce from entries to single result 
+	signal b_web : net_mat(0 to NLEVEL_B-1); 							
   	signal temp_out, temp_mix : STD_LOGIC_VECTOR (NBITS-1 downto 0); 
 
 begin
+	--In this file we reduce each entry side (A and B) to a single result with adders. 
+	--Pipelining is used to match requirements
+
 
+	--*************
 	--Handle A side
 	--Handle shift stage
-	a_1: for i in 0 to (NIN/2)-1 generate				--generate shifts for each entry (do symmetry)
-		a_2: for j in 0 to a_shift_arr(i)(0)-1 generate 	--generate for each shift of this entry
-			a_web(0)(a_shift_arr(i)(4) + j) <= std_logic_vector(unsigned(comb_a_in(i)) sll a_shift_arr(i)(j+1));	--a0 to a4
+	a_1: for i in 0 to (NIN/2)-1 generate							--Generate shifts for each entry (do symmetry)
+		a_2: for j in 0 to a_shift_arr(i)(0)-1 generate 			--Generate wiring for each shift of a specific entry
+			a_web(0)(a_shift_arr(i)(4) + j) <= std_logic_vector(unsigned(comb_a_in(i)) sll a_shift_arr(i)(j+1));						--a0 to a4
 			a_web(0)(A_WIDTH-1 - (a_shift_arr(i)(4) + j)) <= std_logic_vector(unsigned(comb_a_in(NIN-1-i)) sll a_shift_arr(i)(j+1));	--a9 to a5
 		end generate;
 	end generate;
 
-
-	a_3: for k in 0 to NLEVEL_A-2 generate	--generate adders or pipeline for each level	
+	--Handle adder + pipelining stages
+	a_3: for k in 0 to NLEVEL_A-2 generate							--Generate adders or pipeline for each level	
 		a_4: for l in 0 to a_elem_index(k)(ELEM_ADDER)-1 generate
 			a_add: adder port map(a_web(k)(2*l),a_web(k)(2*l +1),a_web(k+1)(l));
 		end generate a_4;
-		a_5: if k = 5 generate		--when number of wire is odd, no need for adder but one wire need to be transmited
+		a_5: if k = 5 generate										--When number of wire is odd, last wire is transmitted to next level
 			a_web(k+1)(a_elem_index(k)(ELEM_ADDER)) <= a_web(k)(2*a_elem_index(k)(ELEM_ADDER));
 		end generate a_5;
-		ap_1: for m in 0 to a_elem_index(k)(ELEM_REG)-1 generate	--register for pipeline
+		ap_1: for m in 0 to a_elem_index(k)(ELEM_REG)-1 generate	--Registers for pipelining
 			a_reg: reg port map(Reset, Clk, '1', a_web(k)(m),a_web(k+1)(m));
 		end generate;
 	end generate a_3;
 
 
+	--*************
 	--Handle B side
 	--Handle shift stage
-	b_1: for i in 0 to (NIN/2)-1 generate				--generate for each entry (do symmetry)
-		b_2: for j in 0 to b_shift_arr(i)(0)-1 generate 	--generate for each shift of this entry
-			b_web(0)(b_shift_arr(i)(4) + j) <= std_logic_vector(unsigned(comb_b_in(i)) sll b_shift_arr(i)(j+1));	--b0 to b4
-			b_6: if i /= 4 generate --no symetry for b4
+	b_1: for i in 0 to (NIN/2)-1 generate							--Generate for each entry (do partial symmetry)
+		b_2: for j in 0 to b_shift_arr(i)(0)-1 generate 			--Generate wiring for each shift of a specific entry
+			b_web(0)(b_shift_arr(i)(4) + j) <= std_logic_vector(unsigned(comb_b_in(i)) sll b_shift_arr(i)(j+1));						--b0 to b4
+			b_6: if i /= 4 generate 																									--no symmetry for b4
 			   b_web(0)(B_WIDTH-1 - (b_shift_arr(i)(4) + j)) <= std_logic_vector(unsigned(comb_b_in(NIN-2-i)) sll b_shift_arr(i)(j+1));	--b8 to b5
 		  end generate;
 		end generate;
 	end generate;
 
-	--Direct wiring for early feedback
+	--Handle direct wiring (shortcut) for early feedback
 	bj_1: for i in 0 to N_DIRECT_JUMP-1 generate	
 		b_web(feedb_jump_index(i)(0))(feedb_jump_index(i)(1)) <= b_web(0)(B_WIDTH-1-i);
 	end generate; 
 
-	--generate adders for each level
-	b_3: for k in 0 to NLEVEL_B-2 generate						
+	--Handle adder + pipelining stages
+	b_3: for k in 0 to NLEVEL_B-2 generate							--Generate adders or pipeline for each level
 		b_4: for l in 0 to b_elem_index(k)(ELEM_ADDER)-1 generate
 			 b_add: adder port map(b_web(k)(2*l),b_web(k)(2*l +1),b_web(k+1)(l));
 		end generate b_4;
-		b_5: if (k = 3) generate		--when number of wire is odd, no need for adder
+		b_5: if (k = 3) generate									--When number of wire is odd, last wire is transmitted to next level
 			b_web(k+1)(b_elem_index(k)(ELEM_ADDER)) <= b_web(k)(2*b_elem_index(k)(ELEM_ADDER));
 		end generate b_5;
-		bp_1: for m in 0 to b_elem_index(k)(ELEM_REG)-1 generate	--register for pipeline
+		bp_1: for m in 0 to b_elem_index(k)(ELEM_REG)-1 generate	--Registers for pipelining
 			b_reg: reg port map(Reset, Clk, '1', b_web(k)(m),b_web(k+1)(m));
 		end generate;
 	end generate b_3;
 
 
-	--Mix A and B for last stages to optimize since B is longer
+	--*************
+	--Add A and B for last stages to optimize, since B is longer than A
 	mix_1: adder port map(a_web(NLEVEL_A-1)(0),b_web(NLEVEL_B-1)(1),temp_mix);
 
 	--Output

SRC/fir_sol/iir_sol.vhd

@@ -1,3 +1,8 @@
+--EPFL
+--DTIS PROJECT
+--Michael Roy
+--December 2012
+
 library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.STD_LOGIC_ARITH.ALL;
@@ -39,22 +44,23 @@ architecture Structural of iir_sol is
 	signal reg_sig : array32_t(0 to NIN-1);
 
 begin
+
+	--In this part we create register for the feedback loop and connect them to the combinational block
+
 
-	--Output <= (others => '0') when Reset = '1' else reg_sig(NIN-1); --connect the output
-	Output <= reg_sig(NIN-1);
+	Output <= reg_sig(NIN-1);	--Output is connect to feedback loop
 
-	regi1: for i in NIN-NPIPE-1 to NIN-2 generate		--generate registers for early feedback	
-  	 regi2: reg port map(Reset,Clk,'1',reg_sig(NIN-1),reg_sig(i));	
+	regi1: for i in NIN-NPIPE-1 to NIN-2 generate		--generate registers for early feedback, NPIPE of them are in parallel to give early feedback (NPIPE register is faster than one distributed)	
+  		regi2: reg port map(Reset,Clk,'1',reg_sig(NIN-1),reg_sig(i));	
 	end generate;
 
-	reg_sig(NIN-NPIPE-2) <= reg_sig(NIN-NPIPE-1);	--make transition
-
+	reg_sig(NIN-NPIPE-2) <= reg_sig(NIN-NPIPE-1);	--make transition between register in parallel and serially
 
-	regi3: for i in 0 to NIN-NPIPE-3 generate		--generate rest of registers and connect them together
+	regi3: for i in 0 to NIN-NPIPE-3 generate		--generate rest of registers and connect them together serially
 			regi4: reg port map(Reset,Clk,'1',reg_sig(i+1),reg_sig(i));	
 	end generate;
 
-	comb: comb_part port map(Reset, Clk, Input,reg_sig(0 to NIN-2),reg_sig(NIN-1));
+	comb: comb_part port map(Reset, Clk, Input,reg_sig(0 to NIN-2),reg_sig(NIN-1));	--instantiate combinational part
 
 end Structural;