Balanced ternary CPU hardware emulator

The architecture and instruction set was designed by mwk for Dragon CTF 2019. Here's the challenge: CPU Adventure 2. The architecture description is also there: SPOILERS.rst

This project implements that CPU on PYNQ FPGA board. There's one notable difference between this project and the original design, namely, division instruction. In CPU Adventure 2 division was implemented by converting from ternary to binary, doing division in binary, and converting back to ternary. In this project I've implemented balanced ternary division directly, hovewer, balanced ternary division works differently from binary division. Given integers a and b the algorithm finds integers q and r such that a = q*b + r and abs(r) is less than or equal to b / 2. For example, dividing 7 by 10 gives q = 1 and r = -3.

Files

Many files are copied from original cpuadventure2 repo: cpuadventure2

• src/: Implementation of CPU. Written in Verilog with Vivado.
• src/tras/: "tras" files, also copied from cpuadventure2
• tricpu.hwh: Vivado file, connects top module with AXI, buttons, leds, etc.
• tricpu.bit: Generated by Vivado.
• main.py: Run this on PYNQ board. It uploads tricpu.bit to FPGA and implements termcalls and hypercalls on AXI.
• term.c, term.so: termios interface, used by main.py
• static/: Those files can be read from CPU with hypercalls.