DynamicTablesPkg/AmlLib: Enumerate memory cacheability and type

AmlCodeGenRdQWordMemory's and AmlCodeGenRdDWordMemory's Cacheable and MemoryRangeType parameters treat specific values as having specific meanings. This change adds enums to map those meanings to their corresponding values. JIRA TEGRAUEFI-2822 Signed-off-by: Jeshua Smith <jeshuas@nvidia.com> Change-Id: I2d4229bdf91db5124cf02df958200afcc1a189e9
NVIDIA · Oct 2, 2023 · 4e29533 · 4e29533
1 parent 1a66bd5
commit 4e29533
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Showing 2 changed files with 39 additions and 6 deletions.
diff --git a/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h b/DynamicTablesPkg/Include/Library/AmlLib/AmlLib.h
@@ -59,6 +59,39 @@ typedef void *AML_DATA_NODE_HANDLE;
 
 #endif // AML_HANDLE
 
+/** Cacheable parameter values
+
+  Possible values are:
+    0-The memory is non-cacheable
+    1-The memory is cacheable
+    2-The memory is cacheable and supports
+      write combining
+    3-The memory is cacheable and prefetchable
+
+**/
+typedef enum {
+  AML_MEMORY_NONCACHEABLE = 0,
+  AML_MEMORY_CACHEABLE    = 1,
+  AML_MEMORY_CACHEABLE_WC = 2,
+  AML_MEMORY_CACHEABLE_PF = 3
+} AML_MEMORY_CACHEABILITY;
+
+/** MemoryRangeType parameter values
+
+  Possible values are:
+    0-AddressRangeMemory
+    1-AddressRangeReserved
+    2-AddressRangeACPI
+    3-AddressRangeNVS
+
+**/
+typedef enum {
+  AML_MEMORY_RANGE_TYPE_MEMORY   = 0,
+  AML_MEMORY_RANGE_TYPE_RESERVED = 1,
+  AML_MEMORY_RANGE_TYPE_ACPI     = 2,
+  AML_MEMORY_RANGE_TYPE_NVS      = 3
+} AML_MEMORY_RANGE_TYPE;
+
 /** Parse the definition block.
 
   The function parses the whole AML blob. It starts with the ACPI DSDT/SSDT

diff --git a/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtPcieLibArm/SsdtPcieGenerator.c b/DynamicTablesPkg/Library/Acpi/Arm/AcpiSsdtPcieLibArm/SsdtPcieGenerator.c
@@ -566,7 +566,7 @@ GeneratePciCrs (
                    IsPosDecode,
                    TRUE,
                    TRUE,
-                   TRUE,
+                   AML_MEMORY_CACHEABLE,
                    TRUE,
                    0,
                    AddrMapInfo->PciAddress,
@@ -575,7 +575,7 @@ GeneratePciCrs (
                    AddrMapInfo->AddressSize,
                    0,
                    NULL,
-                   0,
+                   AML_MEMORY_RANGE_TYPE_MEMORY,
                    TRUE,
                    CrsNode,
                    NULL
@@ -588,7 +588,7 @@ GeneratePciCrs (
                    IsPosDecode,
                    TRUE,
                    TRUE,
-                   TRUE,
+                   AML_MEMORY_CACHEABLE,
                    TRUE,
                    0,
                    AddrMapInfo->PciAddress,
@@ -597,7 +597,7 @@ GeneratePciCrs (
                    AddrMapInfo->AddressSize,
                    0,
                    NULL,
-                   0,
+                   AML_MEMORY_RANGE_TYPE_MEMORY,
                    TRUE,
                    CrsNode,
                    NULL
@@ -718,7 +718,7 @@ ReserveEcamSpace (
              TRUE,
              TRUE,
              TRUE,
-             FALSE,  // non-cacheable
+             AML_MEMORY_NONCACHEABLE,
              TRUE,
              0,
              AddressMinimum,
@@ -727,7 +727,7 @@ ReserveEcamSpace (
              AddressMaximum - AddressMinimum + 1,
              0,
              NULL,
-             0,
+             AML_MEMORY_RANGE_TYPE_MEMORY,
              TRUE,
              CrsNode,
              NULL