Basic features: Vec8f and Vec4f

.cargo/config.toml

@@ -0,0 +1,2 @@
+[build]
+rustflags = ["-C", "target-cpu=native"]

.github/workflows/ci.yaml

@@ -0,0 +1,103 @@
+# borrowed from https://github.com/actions-rs/meta/blob/master/recipes/quickstart.md
+on: [push, pull_request]
+
+name: Continuous integration
+
+jobs:
+  check:
+    name: Check
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v2
+      - uses: actions-rs/toolchain@v1
+        with:
+          profile: minimal
+          toolchain: stable
+          override: true
+      - uses: actions-rs/cargo@v1
+        with:
+          command: check
+
+  check_32bits:
+    name: Check (32 bits; no AVX)
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v2
+      - uses: actions-rs/toolchain@v1
+        with:
+          profile: minimal
+          toolchain: nightly
+          override: true
+          target: i686-unknown-linux-gnu
+      - uses: actions-rs/cargo@v1
+        with:
+          use-cross: true
+          command: check
+          args: --target i686-unknown-linux-gnu -Zdoctest-xcompile
+        env:
+          RUSTFLAGS: -C target-feature=-avx,-avx2
+
+  test:
+    name: Test Suite
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v2
+      - uses: actions-rs/toolchain@v1
+        with:
+          profile: minimal
+          toolchain: stable
+          override: true
+      - uses: actions-rs/cargo@v1
+        with:
+          command: test
+
+  test_32bits:
+    name: Test Suite (32 bits; no AVX)
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v2
+      - uses: actions-rs/toolchain@v1
+        with:
+          profile: minimal
+          toolchain: nightly
+          override: true
+          target: i686-unknown-linux-gnu
+      - uses: actions-rs/cargo@v1
+        with:
+          use-cross: true
+          command: test
+          args: --target i686-unknown-linux-gnu -Zdoctest-xcompile
+        env:
+          RUSTFLAGS: -C target-feature=-avx,-avx2
+
+  fmt:
+    name: Rustfmt
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v2
+      - uses: actions-rs/toolchain@v1
+        with:
+          profile: minimal
+          toolchain: stable
+          override: true
+      - run: rustup component add rustfmt
+      - uses: actions-rs/cargo@v1
+        with:
+          command: fmt
+          args: --all -- --check
+
+  clippy:
+    name: Clippy
+    runs-on: ubuntu-latest
+    steps:
+      - uses: actions/checkout@v2
+      - uses: actions-rs/toolchain@v1
+        with:
+          profile: minimal
+          toolchain: stable
+          override: true
+      - run: rustup component add clippy
+      - uses: actions-rs/cargo@v1
+        with:
+          command: clippy
+          args: -- -D warnings

Cargo.toml

@@ -3,3 +3,10 @@ authors = ["NamorNiradnug"]
 name = "vector-rust-library"
 version = "0.1.0"
 edition = "2021"
+
+[lib]
+name = "vrl"
+
+[dependencies]
+paste = "1.0.14"
+derive_more = "0.99.17"

build.rs

@@ -0,0 +1,16 @@
+use std::env;
+
+fn feature_shortcut(feature: &str) {
+    if env::var("CARGO_CFG_TARGET_FEATURE")
+        .map_or(false, |cfg| cfg.split(',').any(|f| f == feature))
+    {
+        println!("cargo:rustc-cfg={}", feature);
+    } else {
+        println!("cargo:rustc-cfg=no_{}", feature)
+    }
+}
+
+fn main() {
+    feature_shortcut("sse");
+    feature_shortcut("avx");
+}

src/common.rs

@@ -0,0 +1,47 @@
+use std::ops::{Add, AddAssign, Div, DivAssign, Mul, MulAssign, Neg, Sub, SubAssign};
+
+/// Represents a packed vector containing [`ELEMENTS`](SIMDVector::ELEMENTS)
+/// values of type [`Element`].
+///
+/// Converting [`Element`] to [`SIMDVector`] works as `broadcast`, i.e. assigns
+/// the converting value to all elements of the vector.
+///
+/// [`Default::default`] initializes all elements of vector with zero.
+///
+/// All arithmetic operations ([`Neg`], [`Add`], etc) are applied vertically, i.e. "elementwise".
+///
+/// [`Element`]: Self::Element
+pub trait SIMDVector
+where
+    Self: From<Self::Underlying>
+        + From<Self::Element>
+        + Default
+        + Neg<Output = Self>
+        + Add<Self>
+        + Add<Self::Element>
+        + Sub<Self>
+        + Sub<Self::Element>
+        + Mul<Self>
+        + Mul<Self::Element>
+        + Div<Self>
+        + Div<Self::Element>
+        + AddAssign<Self>
+        + AddAssign<Self::Element>
+        + SubAssign<Self>
+        + SubAssign<Self::Element>
+        + MulAssign<Self>
+        + MulAssign<Self::Element>
+        + DivAssign<Self>
+        + DivAssign<Self::Element>, // + [Self::Element; Self::ELEMENTS]
+    Self::Underlying: From<Self>,
+    Self::Element: Add<Self> + Sub<Self> + Mul<Self> + Div<Self>,
+{
+    /// Underlying intrinsic type or tuple of types implementing [`SIMDVector`].
+    type Underlying;
+
+    /// Type of a single element of [`SIMDVector`].
+    type Element;
+
+    /// Number of elements in [`SIMDVector`].
+    const ELEMENTS: usize;
+}

src/lib.rs

@@ -0,0 +1,27 @@
+//! Port (__NOT__ bindings) of Agner Fog's [Vector Class Library](https://github.com/vectorclass/version2) to Rust.
+//! `vrl` stands for **V**ector **R**ust **L**ibrary.
+//!
+//! This is a library for using the SIMD (Single Instruction Multiple Data) instructions on modern
+//! x86 and x86-64 CPUs.
+
+mod common;
+mod macros;
+
+mod vec4f;
+mod vec8f;
+
+mod intrinsics {
+    #[cfg(target_arch = "x86_64")]
+    pub use core::arch::x86_64::*;
+
+    #[cfg(target_arch = "x86")]
+    pub use core::arch::x86::*;
+}
+
+#[cfg(any(sse, doc))]
+pub use vec4f::Vec4f;
+
+#[cfg(any(sse, doc))]
+pub use vec8f::Vec8f;
+
+pub use common::SIMDVector;

src/macros.rs

@@ -0,0 +1,42 @@
+macro_rules! vec_overload_operator {
+    ($vectype: ty, $op_trait: ident, $op_name: ident, $intrinsic: ident, $basic_impl_condition: meta) => {
+        #[cfg($basic_impl_condition)]
+        impl $op_trait for $vectype {
+            type Output = Self;
+            #[inline(always)]
+            fn $op_name(self, rhs: Self) -> Self::Output {
+                unsafe { $intrinsic(self.into(), rhs.into()).into() }
+            }
+        }
+
+        impl $op_trait<<$vectype as SIMDVector>::Element> for $vectype {
+            type Output = Self;
+            #[inline(always)]
+            fn $op_name(self, rhs: <$vectype as SIMDVector>::Element) -> Self::Output {
+                self.$op_name(Into::<Self>::into(rhs))
+            }
+        }
+
+        impl $op_trait<$vectype> for <$vectype as SIMDVector>::Element {
+            type Output = $vectype;
+            #[inline(always)]
+            fn $op_name(self, rhs: $vectype) -> Self::Output {
+                rhs.$op_name(self)
+            }
+        }
+
+        paste::paste! {
+        impl<T> [<$op_trait Assign>]<T> for $vectype
+        where
+            Self: $op_trait<T, Output = Self>,
+        {
+            #[inline(always)]
+            fn [<$op_name _assign>](&mut self, rhs: T) {
+                *self = self.$op_name(rhs);
+            }
+        }
+        }
+    };
+}
+
+pub(crate) use vec_overload_operator;