Fix LQ instruction to support signed offsets

Based on the Power ISA manual sign extended DQ<<4 is added to RA to get source EA.
NationalSecurityAgency · Aug 19, 2024 · 37a35a3 · 37a35a3
1 parent 3b175b9
commit 37a35a3
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diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_common.sinc
@@ -1983,6 +1983,7 @@ dUI16PlusRAOrZeroAddress: val^"("^RA_OR_ZERO^")" is  RA_OR_ZERO & UI_16_s8 [ val
 @ifdef BIT_64
 dsPlusRaAddress: simm_ds(A)	is SIMM_DS & A [simm_ds = SIMM_DS << 2;] {tmp:8 = simm_ds + A;export tmp;} 
 dsPlusRaOrZeroAddress: simm_ds(RA_OR_ZERO)	is SIMM_DS & RA_OR_ZERO [simm_ds = SIMM_DS << 2;] {tmp:8 = simm_ds + RA_OR_ZERO;export tmp;} 
+dqPlusRaOrZeroAddress: simm_ds(RA_OR_ZERO)	is DQs & RA_OR_ZERO [simm_ds = DQs << 4;] {tmp:8 = simm_ds + RA_OR_ZERO;export tmp;}
 @endif
 
 

diff --git a/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc b/Ghidra/Processors/PowerPC/data/languages/ppc_isa.sinc
@@ -1609,8 +1609,8 @@ define pcodeop stdcixOp;
 # ISA-info: lq - Form "DQ" Page 751 Category "LSQ"
 # binutils: power4.d:  +0:	e0 83 00 00 	lq      r4,0\(r3\)
 # binutils: power4.d:  +4:	e0 83 00 00 	lq      r4,0\(r3\)
-:lq RT,A,DQ is $(NOTVLE) & OP=56 & RT & Dp & A & DQ & BITS_0_3=0 & regp [regpset = Dp+1;] { 
-	ea:$(REGISTER_SIZE) = A + sext(DQ:2 << 4);
+:lq RT,dqPlusRaOrZeroAddress, BITS_0_3 is OP=56 & RT & Dp & RA & DQs & dqPlusRaOrZeroAddress & BITS_0_3 & regp [regpset = Dp+1;] {  
+	ea:$(REGISTER_SIZE) = RA + sext(DQs:2 << 4);
 @if ENDIAN == "big"
 	RT = *:$(REGISTER_SIZE) ea;
 	regp = *:$(REGISTER_SIZE) (ea + $(REGISTER_SIZE));