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Vlan Adder module
vlan_adder
v1.0.0
Neelakandan Manihatty Bojan
IP core (HW)
lib/hw/contrib/cores/vlan_adder_v1_0_0/
AXI4-Stream
AXI-Lite
S_AXIS: Slave AXI4-Stream bus, Variable width
M_AXIS: Master AXI4-Stream bus, Variable width
C_M_AXIS_DATA_WIDTH: Data width of the master AXI4-Stream data bus.
C_S_AXIS_DATA_WIDTH: Data width of the slave AXI4-Stream data bus.
C_M_AXIS_TUSER_WIDTH: Data width of the master TUSER bus.
C_S_AXIS_TUSER_WIDTH: Data width of the slave TUSER bus.
C_BASEADDR: Base address value of the core.
C_HIGHADDR: High address value of the core.
This module uses register infrastructure Ver 1.00, please refer to here for more details.
0x0 : ID - Block ID
0x4 : VERSION - Block Version
0x8 : RESET - Reset bit to reset counters
0xc : FLIP - Returns the negative value of a written register
0x10 :DEBUG - Debug Register
0x14 : COUNTERIN - Total number of incoming packets
0x18: COUNTEROUT - Total number of outgoing packets
0x1c: SMIN - Register that holds the Vlan tag to be inserted
The function of this block is to insert vlan tags to all packets coming through a specific port. All the packets sent through the nf2 or nf3 physical interface will be appended with VLAN tags. The vlan-tagged packets can come out through the nf0 or nf1 (or both) physical interface based on the register configuration set in the nic_output_port_lookup (v4). Currently the tag that is inserted into the packets can be configured through the register.