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Design is Unit instance (hilevel netlist). From this instance it is possible to generate target HDL/IPcore. Or it can be simulated.
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hwt.interfaces - Collection of most essential interfaces like Signal, Clk, Rst, Rst_n...
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hwt.serializer - Converters from internal representation to VHDL/Verilog/SystemC/IPcore/...
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hwt.simulator - RTL based simulator and simulator utils.
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hwt.synthesizer - Tools for generating of internal representation from HWT hw description.
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hwt.code - Contains most of code operations used in HWT hw descriptions like:
- If, Switch and other statements,
- arithmetic operators and functions like slr, isPow2, log2ceil
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hwt.hdl - Classes which representing hdl structures like Entity, Architecture, RtlSignal, hdl types, etc. Object of these classes we call internal representation of HWT. Most of this module is quite low level but there are some part which you will surely use:
- hwt.hdl.typeShortcuts - this file contains definitions of most used hdl types which can be used in HWT hw descriptions
- hwt.hdl.constants - Most used constants like Time, Direction, etc...
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hwt.pyUtils - general purpose python utils
HdlType definitions are stored in hwt.hdl.types. Operators and conversions are defined on HdlType class. This methods are called from RtlSignal/Signal/Value instances. HdlType instance is available in _dtype property of RtlSignal/Signal/Value. Each HdlType class has also specific Value class for example HdlType Bits has Value class BitsVal.
For user specified types may also require to specify serialization method for type and type value in serializer class.
There are plenty of examples and real designs in hwtLib. Most simple have entry level documentation.