- Metaprogramming (Hardware Construction Language HCL, templatization) + HLS.
- Simulator API, UVM
- Buildtool, IP core generator
- The lower layer (IR, HDL serializers) is a shield against a problems related to VHDL/Verilog. It is checking for correctness and synthetisability and removing specific of HDLs.
- The system level and HLS layer allows you to quickly build desing generators with advance optimisation techniques of your choice.
- Simulator API and it's UVM simulation environment is just python object with C++ binding. This makes it easy to use while not sacrificing performance.
- Rich type system can describe also data locality and packet features. This significantly simplifies configuration of component which are working with packets or any data over remote bus.
- HWT is not compiler nor transpiler but it is actually a core library. It contains only necessary stuff and you can can modify/extend any part any time. Because the word of HW developement is always full of unexpected situations.
- Hardware Construction Language (HCL) (example simple, showcase). It is somewhere between HLS and HDL. It offers HLS style of coding but at the same time it allows you to manipulate HDL objects. This means it is a little bit slower to write a prototype than you would in HLS, but you always know what, how and why is happening.
- Digital circuit simulator with UVM like verification environment (example usage CAM, structWriter_test.py)
- Tools for static analysis (resourceAnalyzer, example usage cntr_test.py)
- Serializers to export HWT designs into multiple target HDLs (verilog, VHDL, system-c, IP-core packager, hwt itself...)
HWT uses hilevel-netlists for internal representation of target design. Optimized netlists are generated from usual code statements, function calls, statements etc (hw processes are automatically resolved). This netlist is easy to use and easy to modify or analyse by user if there is something missing in main library. Also serialization modes allows to tweaks how component should behave during serialization.
HWT performs no HLS planing or schedueling. HWT is also good as API for code generating by more advanced tools. Hierarchy of components/interfaces/types is not limited. User specifed names are checked for collision with target language.
HWT designs are objects. No specific compiler execution is required, just run python3, import the thing and use to_rtl metod or other (take a look at examples).
This library is a regular python package. You can install it using:
# system-wide, use -u for local use only
sudo pip3 install hwt
# or directly from git
pip3 install --upgrade --force-reinstall --no-cache-dir -r https://raw.githubusercontent.com/Nic30/hwt/master/doc/requirements.txt git+https://github.com/Nic30/hwt.git@master#egg=hwt
Then you are able to use functions and classes defined in the hwt library from a python console or script. Installation of hwtLib is recomended as it contains common interfaces, agents, components etc...
- Where is the entry point of the compiler?
- This is not a compiler, it is library of the objects which can be converted to Verilog/VHDL and back.
- How do I get Verilog/VHDL?
- Use
to_rtlmethod example
- Use
- How do I define my interface type, protocol and simulation agent?
- Derive from any Interface class. example
- I do have c structure of UDP header, how do I send/recieve UDP packet over AXI-stream interface?
- Define HStruct type composed of eth_header_t, IPv4_header_t and HStream(uint8_t) and use AxisFrameGen. There is and example of ping responder
- autofpga - C++, A utility for Composing FPGA designs from Peripherals
- 💀 baremetal - Python, simple HCL
- BinPy - Python, An electronic simulation library
- 💀 pervognsen/Bitwise - Python, HDL which translates python directly
- 💀 jamesjiang52/Bitwise - Python, simple HCL.
- blarney - Haskell, HCL
- bsc - Haskell, C++, BSV - Bluespec Compiler
- Cement HDL/CmtHDL - Rust, eHDL
- chisel - 2012-?, Scala, HCL
- Chips-2.0 - , , FPGA Design Suite based on C to Verilog design flow
- circt - 2020-?, C++/LLVM, compiler infrastructure
- circuitgraph - Tools for working with circuits as graphs in python
- concat - 2016-?, Haskell, Haskell to hardware
- DUH - JS, simple convertor between verilog/scala/ipxact
- DFiant 2019-?, Scala, dataflow based HDL
- edalize - 2018-?, Python, abstraction layer for eda tools
- garnet -2018-?, Python, Coarse-Grained Reconfigurable Architecture generator based on magma
- hammer - 2017-?, Python, Highly Agile Masks Made Effortlessly from RTL
- heterocl - 2017-?, C++, A Multi-Paradigm Programming Infrastructure for Software-Defined Reconfigurable Computing
- hoodlum - 2016-?, Rust, HCL
- ILAng - modeling and verification platform for SoCs where Instruction-Level Abstraction (ILA) is used as the formal model for hardware components.
- 💀 jhdl - ?-2017, C++ Verilog/VHDL -> systemC, prototype
- Kactus2 - IP-core packager
- kratos - C++/Python, hardware generator/simulator
- lgraph - C, generic graph library
- llhd - Rust, HCL
- livehd - mainly C++, An infrastructure designed for Live Hardware Development.
- Lucid HDL in Alchitry-Labs - Custom language and IDE inspired by Verilog
- magma - 2017-?, Python, HCL
- amaranth/migen - 2013-?, Python, HCL
- mockturtle - logic network library
- moore - Rust, HDL -> model compiler
- msdsl - Python, real number model -> verilog
- MyHDL - 2004-?, Python, Process based HDL
- Amaranth HDL -, Python, (previously nMigen) A refreshed Python toolbox for building complex digital hardware
- OpenTimer - , C++, A High-Performance Timing Analysis Tool for VLSI Systems
- percy - Collection of different synthesizers and exact synthesis methods for use in applications such as circuit resynthesis and design exploration.
- PyChip-py-hcl - , Python, Chisel3 like HCL
- pygears - , Python, function style HDL generator
- PyMTL3 2018-?
- PyMTL - 2014-?, Python, Process based HDL
- PipelineC - 2018-?, Python, C++ HLS-like automatic pipelining as a language construct/compiler
- PyRTL - 2015-?, Python, HCL
- Pyverilog - 2013-? Python-based Hardware Design Processing Toolkit for Verilog HDL
- rogue , C++/Python - Hardware Abstraction & Data Acquisition System
- rohd, 2023-?, dart, HCL
- sail 2018-?, (OCaml, Standard ML, Isabelle) - architecture definition language
- 💀 SFGen - Python, arithmetic function generator
- spatial - Scala, an Argon DSL like, high level abstraction
- SpinalHDL - 2015-?, Scala, HCL
- Silice - ?, C++, Custom HDL
- 💀 SyDpy - ?-2016, Python, HCL and verif. framework operating on TML/RTL level
- systemrdl-compiler - Python,c++, register description language compiler
- UHDM - C++ SystemVerilog -> C++ model
- 💀 Verilog.jl - 2017-2017, Julia, simple Julia to Verilog transpiler
- veriloggen - 2015-?, Python, Verilog centric HCL with HLS like features
- 💀 wyre - 2020-2020, Mupad, Minimalistic HDL
- phi - 2019-?, custom language, llvm based compiler of custom hdl
- prga - 2019-?. Python, prototyping platform with integrated yosys
- Hardcaml - OCaml, HCL
- magia-hdl - 2023-?, Python, HCL
- Metron - C++, C++ -> SystemVerilog syntax translator
- IR - Internal Representation
- HDL - Hardware Design Languge (Lang. construct maps directly to specific HW part)
- eHDL - Embedded HDL (HDL construct avare source code generator)
- HCL - Hardware Construction Language (User code constructs IR. IR can be directly transipled to HDL)
- HLS - High Level Synthesis (User code is translated to IR. IR is compiled to HDL IR in multiple complex steps, typically contains scheduling, arch. mapping etc.)
- fusesoc - package manager and a set of build tools for FPGA/ASIC development
- OpenSTA - a gate level static timing verifier
- RePlAce - global placement tool
- verilator - Verilog -> C/C++ simulator
- vtr-verilog-to-routing
- yosys - RTL synthesis framework
- UHDM - SV -> C++
- litex - Buildsystem for migen
- loam - Buildsystem for magma
- vivado-boards - Vivado XML/TCL files with board description
- nmigen-boards - board and connector meta fo nmigen
- computer-engineering-resources - list of conferences and hardware projects